Samsung Electronics Co Ltd v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2020-01022
• Patent #: 6,781,226
• Filed: May 29, 2020
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 13, 14, 16-22, 23, and 25-30

2. Patent Overview

• Title: Stacked Processor Module
• Brief Description: The ’226 patent discloses a processor module comprising multiple integrated circuit dies (e.g., a microprocessor, memory, and a programmable array like an FPGA) that are vertically stacked. The dies are electrically interconnected using through-silicon contacts (TSVs) distributed across their surfaces to improve performance and enable rapid reconfiguration.

3. Grounds for Unpatentability

Ground 1: Claims 13, 14, 16-21, and 25-30 are obvious over Koyanagi in view of Cooke.

• Prior Art Relied Upon: Koyanagi (Koyanagi et al., Future System-on-Silicon LSI Chips, IEEE 1998) and Cooke (Patent 5,970,254).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Koyanagi taught a universal three-dimensional (3D) integration technology for vertically stacking different types of bare dies—such as microprocessors and memory (SRAM/DRAM)—using a high density of TSVs ("buried interconnections") to increase connectivity and system speed. Cooke disclosed a reconfigurable processor system containing a standard processor, FPGA logic, and a "vertical stack" of memory planes, but provided few details on the stacking method. Petitioner asserted that combining these references renders independent claim 13 obvious by using Koyanagi's detailed 3D stacking method to implement the functional components of Cooke's reconfigurable system. The resulting combination taught a stack of a programmable array (FPGA from Cooke), a processor (from Cooke), and memory (from Cooke), all electrically coupled via TSVs as taught by Koyanagi. The "means for reconfiguring the programmable array within one clock cycle" limitation was met because Koyanagi’s high-density TSVs provided the high-bandwidth data path necessary to achieve the "nearly instantaneous reconfiguration" in a single cycle described by Cooke.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Koyanagi’s universal 3D integration scheme with Cooke’s reconfigurable architecture to achieve the well-known benefits of 3D stacking. These benefits included miniaturization, lower power consumption, and improved performance by solving the interconnect delay problems inherent in 2D FPGA-based systems.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because Cooke already suggested a stacked architecture, and Koyanagi provided a detailed, broadly applicable, and well-documented method for stacking heterogeneous dies to improve performance, directly addressing the goals of Cooke's system.

Ground 2: Claims 13, 14, 16-21, 22, 23, and 25-29 are obvious over Bertin in view of Cooke.

• Prior Art Relied Upon: Bertin (Patent 6,222,276) and Cooke (Patent 5,970,254).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground presented a similar argument to Ground 1, substituting Bertin for Koyanagi. Petitioner contended that Bertin also disclosed a universal 3D integration scheme for stacking various chip types, including logic chips, microprocessors, and memory, using "through-chip conductors" (TSVs) distributed across the die surface. Petitioner argued that because an FPGA (from Cooke) is a type of logic chip, a POSITA would find it obvious to apply Bertin's stacking technology to the components of Cooke's system. This combination allegedly disclosed the claimed stacked module comprising a programmable array, processor, and memory. The high number of interconnects taught by Bertin provided the wide data port structure corresponding to the "means for reconfiguring...within one clock cycle" function, enabling the single-cycle data transfer described in Cooke. The arguments for dependent claims largely mirrored those made under Ground 1, citing Bertin's disclosure of die thinning and through-chip conductors traversing the die thickness.
  • Motivation to Combine: A POSITA would be motivated to apply Bertin’s 3D integration teachings to Cooke’s reconfigurable system to achieve high system packing densities, improved performance through high-speed inter-chip communication, and better heat dissipation, all of which were known advantages of 3D stacking.
  • Expectation of Success: The expectation of success was high, as Cooke suggested a stacked system and Bertin provided a detailed, universal method for stacking the exact types of components (processor, memory, logic/FPGA) that comprised Cooke's system.

4. Key Claim Construction Positions

• "means for reconfiguring the programmable array within one clock cycle" (Claim 13) and "means for updating the plurality of configuration logic cells within one clock cycle" (Claim 22):
  • Petitioner argued these are means-plus-function limitations under pre-AIA 35 U.S.C. §112, ¶ 6.
  • Function: Reconfiguring the programmable array (or updating its logic cells) within a single clock cycle.
  • Corresponding Structure: A wide configuration data port that interconnects a stacked memory die and an FPGA die, using contact points (TSVs) distributed throughout the surfaces of the dies. Petitioner contended this structure is what enables the high-bandwidth data transfer required for single-cycle reconfiguration, distinguishing it from prior art narrow, peripheral data ports.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise its discretion to deny institution under either §325(d) or §314(a).
  • §325(d) (Becton Dickinson Factors): The petition asserted that the prior art references (Koyanagi, Bertin, Cooke) and the specific obviousness combinations were never considered by the examiner during prosecution. Therefore, the petition raised new arguments and art, weighing strongly in favor of institution.
  • §314(a) (Fintiv Factors): Petitioner contended that the co-pending district court litigation was in its very early stages. At the time of the anticipated institution decision, key events like the claim construction hearing and summary judgment motions would still be months away, meaning the court would not yet have invested significant resources. This lack of advancement in the parallel proceeding weighed in favor of instituting the IPR.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 13, 14, 16-22, 23, and 25-30 of the ’226 patent as unpatentable.