PTAB

IPR2020-01219

Xilinx Inc v. Analog Devices Inc

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Adaptive Delay Element for PVT Compensation in a Comparator
  • Brief Description: The ’659 patent relates to a delay element within a comparator of a successive approximation register analog-to-digital converter (SAR ADC). The delay element is designed to dynamically adapt its delay to counteract process, voltage, and temperature (PVT) variations in the circuit environment, thereby stabilizing the comparator’s throughput.

3. Grounds for Unpatentability

Ground 1: Anticipation over Yoshioka - Claims 5-6 and 9 are anticipated by Yoshioka under 35 U.S.C. §102.

  • Prior Art Relied Upon: Yoshioka (Masato Yoshioka, et al., A 10-b 50-MS/s 820-µW SAR ADC With On-Chip Digital Calibration, IEEE Transactions on Biomedical Circuits and Systems, Vol. 4, No. 6 (2010)).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yoshioka discloses a SAR ADC with an "internal clock control to compensate for PVT variations," which functions as the claimed adaptive delay device. Yoshioka’s delay controller adjusts its delay time (Td) based on the number of clock cycles (N) detected during a conversion phase. If N exceeds a target value (indicating the circuit is running faster due to PVT effects), Td is increased. Conversely, if N is below the target (circuit running slower), Td is decreased. Petitioner asserted this directly teaches the core limitation of varying delay inversely in response to PVT effects on other circuit components, anticipating independent claim 5 and method claim 9. Dependent claim 6 was also argued to be disclosed by Yoshioka's capacitive elements and switches.

Ground 2: Obviousness over Ajit and Applicant Admitted Prior Art - Claims 1 and 5 are obvious over Ajit in view of AAPA under 35 U.S.C. §103.

  • Prior Art Relied Upon: Ajit (Patent 7,268,595) and Applicant Admitted Prior Art (AAPA), which is Figure 1 of the ’659 patent.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner stated that AAPA discloses a conventional SAR ADC comparator with a fixed delay element (a series of inverters) to time a latch signal. Ajit teaches a PVT compensator circuit that functions as an adaptive delay element, adjusting delay inversely to PVT conditions to ensure stable circuit performance. Specifically, Ajit's circuit increases delay when an input signal falls quickly (a PVT effect) and decreases delay when it falls slowly.
    • Motivation to Combine: A POSITA would recognize the known problem of PVT variations impacting circuits with fixed delays, as shown in AAPA. A POSITA would combine the teachings by replacing the fixed delay element of AAPA with the adaptive delay element from Ajit. This modification would be a simple substitution of one known element for another to achieve the predictable result of a circuit that compensates for PVT variations.
    • Expectation of Success: The combination involved applying a known solution (adaptive delay) to a known problem (PVT sensitivity) and would have yielded predictable results.

Ground 3: Obviousness over Yoshioka, AAPA, and Fiscus - Claims 3-4 are obvious over Yoshioka in view of AAPA and Fiscus under §103.

  • Prior Art Relied Upon: Yoshioka, AAPA, and Fiscus (Patent 6,628,558).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds on the combination of Yoshioka and AAPA from other grounds, which establishes a baseline SAR ADC with an adaptive delay element. Fiscus was introduced for its teaching of a proportional to absolute temperature (PTAT) voltage generator and current source, which provides a current proportional to the temperature of circuit components.
    • Motivation to Combine: The ’659 patent itself acknowledges that PTAT circuits are known for responding to temperature variations. A POSITA, seeking to make the adaptive delay of Yoshioka more robust across all PVT corners, would be motivated to incorporate Fiscus's specific temperature compensation technology. This would involve modifying the inverters in Yoshioka’s delay controller to implement the PTAT-controlled delay stage from Fiscus, yielding an adaptive delay element responsive to process, voltage, and temperature.
    • Expectation of Success: Leveraging known PTAT technology to improve temperature compensation in an existing adaptive circuit was a known design choice that would lead to the predictable result of enhanced temperature stability.

  • Additional Grounds: Petitioner asserted additional anticipation challenges against claims 9-11 based on Ajit and obviousness challenges against claims 1-2, 7-8, and 10 based on combinations of Yoshioka, Fiscus, and AAPA. These grounds relied on similar theories of direct disclosure or the substitution of known adaptive delay elements for fixed ones and enhancing them with known temperature compensation circuits.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-11 of Patent 8,487,659 as unpatentable.