Apple Inc v. Universal Secure Registry LLC

1. Case Identification

• Case #: IPR2020-01225
• Patent #: 8,860,227
• Filed: August 11, 2020
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): STATS ChipPAC PTE. Ltd.
• Challenged Claims: 1-5, 8-10, 13, and 14

2. Patent Overview

• Title: Semiconductor Package and Method for Manufacturing the Same
• Brief Description: The ’227 patent relates to fan-out wafer level packages (FO-WLP) for semiconductors. It discloses a package structure intended to mitigate package warpage by defining a specific relationship between the coefficient of thermal expansion (CTE) of a molding compound and the CTE of a redistribution layer (RDL) formed upon it.

3. Grounds for Unpatentability

Ground 1: Obviousness over Mizukoshi and Lin - Claims 1-5, 8-10, 13, and 14 are obvious over Mizukoshi in view of Lin.

• Prior Art Relied Upon: Mizukoshi (Application # 2010/0171221) and Lin (Patent 8,264,076).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Mizukoshi discloses a FO-WLP with a semiconductor chip, molding compound, and an RDL, teaching all limitations of independent claim 1 except for the specific CTE relationship. Lin was argued to supply this missing element. Lin addresses the same warpage problem in similar packages and explicitly teaches that setting the CTE of the encapsulant (molding compound) to be higher than the CTE of the RDL's dielectric material counteracts warpage. Dependent claims were argued to be obvious as they recited conventional FO-WLP features also found in the prior art.
  • Motivation to Combine: A POSITA would combine Mizukoshi with Lin because both references address the well-known and critical problem of package warpage in FO-WLPs. Petitioner asserted that Lin provides a known solution (managing CTEs) to the exact problem faced when implementing Mizukoshi's package structure, making the combination a predictable application of established design principles to improve yield and reliability.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in applying Lin's CTE management teaching to Mizukoshi's structure, as it involved using conventional materials with known properties to achieve a predictable physical result (reduced warpage).

Ground 2: Obviousness over Lee and Lin - Claims 1-5, 8-10, 13, and 14 are obvious over Lee in view of Lin.

• Prior Art Relied Upon: Lee (Patent 8,723,313) and Lin (Patent 8,264,076).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Lee discloses a FO-WLP structure substantially similar to that claimed, including a chip embedded in a molding compound with an RDL formed thereon. As with Mizukoshi, Lee addresses package reliability but does not explicitly teach the claimed CTE relationship. The argument for combining with Lin was identical to Ground 1: Lin provides the missing CTE relationship as a known solution to the warpage problem inherent in Lee's disclosed package structure.
  • Motivation to Combine: The motivation mirrored that of Ground 1. A POSITA seeking to improve the manufacturability and reliability of Lee's package by reducing warpage would look to known solutions in the art, such as the CTE balancing taught by Lin, to solve this known industry problem.
  • Expectation of Success: Petitioner's argument for an expectation of success was the same, asserting the combination involves applying a known engineering principle (CTE matching) to a known package architecture to achieve a predictable outcome.

Ground 3: Obviousness over Chung - Claims 1-5, 8-10, 13, and 14 are obvious over Chung.

• Prior Art Relied Upon: Chung (Patent 8,633,594).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chung, by itself, renders the challenged claims obvious. Chung discloses a FO-WLP structure with all the claimed structural elements and directly addresses warpage by teaching that the molding material and the insulating layer (RDL dielectric) should have CTEs that are "close to each other." Petitioner contended that making the molding compound's CTE slightly higher than the RDL's CTE, as claimed, would be an obvious and predictable design choice for a POSITA optimizing the warpage characteristics based on Chung's disclosure.
  • Motivation to Combine (Implicit): The motivation was presented as inherent in Chung's own disclosure. A POSITA implementing Chung's teaching to select materials with "close" CTEs would be motivated to experiment with minor variations, including making one CTE slightly higher than the other, as a matter of routine optimization to find the ideal balance for warpage control.
  • Expectation of Success: A POSITA would expect that slightly adjusting the CTEs of the materials as guided by Chung's general principle would successfully control warpage, as this is a fundamental and well-understood concept in semiconductor packaging design.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §325(d), asserting that the primary references (Mizukoshi, Lee, Lin, and Chung) were not previously considered during prosecution and present materially different art and arguments than what was before the Examiner.
• Petitioner also contended that discretionary denial under the Fintiv factors was unwarranted. It highlighted that the co-pending district court litigation was in its early stages, with no trial date set, no substantive discovery completed, and no claim construction orders issued. Petitioner argued this posture ensured that an IPR would be a more efficient and timely resolution of the invalidity dispute compared to the district court.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 8-10, 13, and 14 of the ’227 patent as unpatentable.