Intel Corp v. FG SRC LLC

1. Case Identification

• Case #: IPR2020-01449
• Patent #: 7,149,867
• Filed: August 10, 2020
• Petitioner(s): Intel Corporation
• Patent Owner(s): FG SRC LLC
• Challenged Claims: 1-19

2. Patent Overview

• Title: Data Prefetch in a Reconfigurable Hardware System
• Brief Description: The ’867 patent describes enhancing memory bandwidth and efficiency in reconfigurable hardware, such as Field Programmable Gate Arrays (FPGAs). The invention centers on a configurable "data prefetch unit" designed to move only the data required for a specific computation from a slower memory to a faster memory before it is needed by the processor.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zhang and Gupta - Claims 1-2, 4-8, and 13-19 are obvious over Zhang in view of Gupta.

• Prior Art Relied Upon: Zhang (a 1997 IEEE paper titled "Architectural Adaptation of Application-Specific Locality Optimizations") and Gupta (a 2000 IEEE paper titled "Architectural Adaptation in AMRM Machines").
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Zhang taught the core elements of the invention, including a reconfigurable processor architecture with a customizable memory hierarchy and a data prefetcher. Zhang’s prefetcher is implemented in programmable logic, integrated with an L1 cache, and uses dynamic scatter/gather techniques to retrieve only the necessary computational data (e.g., specific matrix elements) from a second memory (L2 cache or main memory). This process operates independently and in parallel with the main processor to hide memory latency. Gupta was presented as disclosing a prototype implementation of the architecture described in Zhang. It detailed an "AMRM" board with a prefetch unit positioned between the L1 and L2 caches, explicitly teaching that memory hierarchy activity like prefetching proceeds "in parallel with CPU computation."
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references because they originated from the same research project (MORPH/AMRM), shared a common author, and addressed the same problem of improving memory efficiency in reconfigurable hardware. Gupta explicitly cited Zhang and described its prototype as a physical implementation of Zhang’s conceptual architecture. Therefore, a POSITA would have looked to Gupta to understand a practical way to implement the framework taught by Zhang.
  • Expectation of Success: The combination would have yielded predictable results, as Gupta was a direct implementation of the system architecture proposed in Zhang.

Ground 2: Obviousness over Zhang, Gupta, and Chien - Claims 3 and 9-12 are obvious over Zhang in view of Gupta and Chien.

• Prior Art Relied Upon: Zhang, Gupta, and Chien (a 1996 IEEE paper titled "MORPH: A System Architecture for Robust Higher Performance Using Customization").
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination of Zhang and Gupta and added Chien to address limitations related to multiprocessor systems and shared external memory. Petitioner asserted that Zhang and Gupta taught a reconfigurable processor with a data prefetch unit that writes processed data from an on-processor memory (L1 cache) back to a lower-level memory (L2 cache or main memory). Chien, which described the foundational MORPH architecture for the same research project, disclosed various multiprocessor configurations, including one using an external "global shared memory" common to multiple processing elements. The incremental teaching from Chien was its disclosure of this external, common memory configuration.
  • Motivation to Combine: A POSITA would have been motivated to incorporate Chien's teachings because all three references stemmed from the same project. Zhang expressly contemplated multiprocessor systems and cited Chien for architectural details. To implement the Zhang/Gupta prefetching system in a multiprocessor context, a POSITA would have naturally looked to Chien’s compatible shared memory architecture as a known and advantageous approach, providing predictable benefits in programmability.
  • Expectation of Success: A POSITA would have had a high expectation of success in combining the teachings, as the references described compatible components within the same overarching system architecture.

4. Key Claim Construction Positions

• "reconfigurable processor": Petitioner proposed this term be construed to mean "a computing device that contains reconfigurable components such as FPGAs and can, through reconfiguration, instantiate an algorithm as hardware." This construction was central to mapping the prior art's discussion of FPGAs and programmable logic to the claims.
• "data prefetch unit": Petitioner proposed this term be construed as "a functional unit that moves data between members of a memory hierarchy." This broad construction was used to argue that the prefetchers described in Zhang and Gupta, which move data between L1, L2, and main memory, met the claim limitation.

5. Arguments Regarding Discretionary Denial

• Against §314(a) Denial (Fintiv): Petitioner argued against discretionary denial based on a parallel district court proceeding. It asserted that: (1) discovery in the parallel case was stayed and the case was in its infancy with no trial date set; (2) the IPR challenges all 19 claims, whereas the district court case involved fewer claims, making the IPR more efficient; and (3) Petitioner stipulated it would not pursue the same invalidity grounds in district court if the IPR was instituted.
• Against §325(d) Denial: Petitioner argued that denial was unwarranted because the petition raised new invalidity challenges based on prior art not previously considered by the USPTO. The primary references (Zhang, Gupta, and Chien) were never before the Examiner during prosecution. Furthermore, these references were materially different from the art considered in a prior IPR filed by another party (Amazon), which the Board had denied based on an incorrect claim construction and different prior art.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-19 of the ’867 patent as unpatentable under 35 U.S.C. §103.