Qualcomm Inc v. Monterey Research LLC

1. Case Identification

• Case #: IPR2020-01492
• Patent #: 6,651,134
• Filed: August 20, 2020
• Petitioner(s): Qualcomm Incorporated
• Patent Owner(s): Monterey Research, LLC
• Challenged Claims: 1-7, 9-21

2. Patent Overview

• Title: Memory Devices with Fixed Length Non Interruptible Burst
• Brief Description: The ’134 patent describes a memory circuit that performs burst read/write operations. The core asserted novelty relates to the generation of a "predetermined" number of internal address signals being "non-interruptible" once initiated in response to a single external address.

3. Grounds for Unpatentability

Ground 1A: Anticipation over Schaefer - Claims 1-5, 7, 9-10, 12-18, 20, and 21 are anticipated by Schaefer.

• Prior Art Relied Upon: Schaefer (Patent 5,600,605).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Schaefer, which discloses a synchronous dynamic random access memory (SDRAM), teaches every limitation of the challenged claims. Specifically, Schaefer’s mode of operation using a “READ with AUTO-PRECHARGE” command was asserted to be non-interruptible because it explicitly states that “[t]he user is not allowed to issue another command until the precharged time (tRP) is completed.” Petitioner contended this prohibition covers the entire burst operation. Furthermore, Schaefer’s disclosure of a programmable mode register to set burst lengths of 2, 4, 8, or a full page was argued to meet the limitation of generating a “predetermined number” of internal address signals, as the burst length is fixed before the read command is issued.
  • Key Aspects: This ground relied on a claim construction where "predetermined" means the burst length is fixed prior to the receipt of a read/write command, but not necessarily at the time of manufacture.

Ground 1B: Obviousness over Schaefer and Fujioka - Claims 1-7, 9-10, and 12-21 are obvious over Schaefer in view of Fujioka.

• Prior Art Relied Upon: Schaefer (Patent 5,600,605) and Fujioka (Patent 6,185,149).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative to Ground 1A, addressing a narrower potential claim construction where "predetermined" means the burst length is fixed at the time of manufacture. While Schaefer taught programming burst length via a mode register after power-up, Fujioka was cited for its teaching of setting burst length "during the fabrication process" using methods like wire bonding. Petitioner argued that Fujioka’s method of using bond options to set burst length was a well-known alternative to using a mode register.
  • Motivation to Combine: A POSITA would combine Fujioka’s manufacturing-time programmability with Schaefer’s memory architecture to gain known advantages. These included reducing circuitry complexity, lowering initialization time and power consumption, and improving manufacturing inventory control. The applicant for the ’134 patent had also admitted during prosecution that using bond options was a well-known technique.
  • Expectation of Success: Success was expected because Fujioka taught that its bond-option circuitry generated the same type of internal burst-length signal as a mode register, making it a straightforward and predictable substitution into Schaefer’s design.

Ground 2A: Obviousness over Schaefer and Lysinger - Claim 11 is obvious over Schaefer in view of Lysinger.

• Prior Art Relied Upon: Schaefer (Patent 5,600,605) and Lysinger (Patent 5,784,331).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground specifically targeted claim 11, which added the limitation that the number of internal address signals is chosen to meet criteria for "sharing address and control busses." Schaefer taught that during its burst operations, external address and control busses are freed up. However, Schaefer did not explicitly teach using this freed-up capacity to perform other tasks. Lysinger was introduced for its express teaching of using the "timing window" created by freed-up busses during a burst operation to perform other functions, such as "accessing other memory devices or interfacing with the microprocessor."
  • Motivation to Combine: Schaefer was directed at improving speed and data throughput by eliminating wasted clock cycles. A POSITA seeking to further this goal would have been motivated to implement Lysinger's strategy. Using the bus capacity freed up by Schaefer’s architecture to perform parallel tasks, as taught by Lysinger, was an obvious way to further increase overall system throughput.
  • Expectation of Success: Lysinger taught that success depended on the burst being long enough to create a sufficient timing window for a new address to propagate. A POSITA would have understood that Schaefer’s programmable burst length could be set to a sufficient length (e.g., eight cycles) to ensure this success, making the combination straightforward.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 11 (Ground 2B) based on Schaefer in view of Lysinger and Fujioka, relying on the same motivations and mappings described in the grounds above.

4. Key Claim Construction Positions

• “predetermined number of ... internal address signals” / “fixed burst length”: This was the most critical construction. Petitioner advanced two alternative constructions to preemptively counter Patent Owner’s likely positions.
  • First Construction: Argued that "predetermined" or "fixed" should mean determined prior to receipt of the external command signals that initiate the burst, but after manufacturing. Under this view, programming a mode register as in Schaefer meets the limitation. Grounds 1A and 2A relied on this construction.
  • Second Construction: Alternatively, if "predetermined" required the value to be fixed prior to initialization/power-up (i.e., at manufacture), Petitioner argued the claims were still obvious. Grounds 1B and 2B, which added Fujioka's teaching of setting burst length via bond options during fabrication, were designed to satisfy this narrower construction.
• “non-interruptible”: Petitioner adopted the construction from a related litigation, meaning "cannot be stopped or terminated once initiated until the fixed number of internal addresses has been generated." Petitioner argued Schaefer’s "AUTO-PRECHARGE" feature, which prohibits new commands for a set duration, met this requirement.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that the grounds in this petition were not cumulative over those in a related case, IPR2020-00985, and therefore discretionary denial under §325(d) was inappropriate. The key distinctions asserted were the reliance on a different primary prior art reference (Schaefer in this petition versus Wada in IPR2020-00985) and the application of an alternative claim construction for "predetermined" that was not advanced in the other petition.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-7 and 9-21 of the ’134 patent as unpatentable.