PTAB

IPR2020-01564

Xilinx Inc v. Analog Devices Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Signal Conditioning System with Offset Signal Sensor
  • Brief Description: The ’750 patent discloses randomly interleaved analog-to-digital converter (ADC) systems that use an offset signal sensor to correct for offset and/or gain mismatches between the multiple ADCs. The system employs a random clock to decorrelate the input signal, which helps isolate the ADC's internal offset for correction.

3. Grounds for Unpatentability

Ground A: Anticipation of Claims 1-2 and 4-6 by Jamal

  • Prior Art Relied Upon: Jamal (S. M. Jamal et al., “A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration,” IEEE Journal of Solid-State Circuits, Dec. 2002).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Jamal, which discloses a time-interleaved ADC with a "random-chopper-based offset calibration scheme," anticipates every limitation of claims 1-2 and 4-6. Jamal's system includes multiple converters and an offset calibration method for each. Critically, Petitioner asserted that Jamal’s use of a "pseudorandom binary signal" to chop the input signal meets the "random clock" limitation of claim 1. This argument relied in part on the Patent Owner's apparent interpretation of this term in parallel district court litigation. Jamal's offset calibration system, which uses an accumulator and summer in a feedback loop to force the average accumulator input to zero, was argued to be the claimed "first offset sensor."
    • Key Aspects: For dependent claims, Petitioner contended Jamal’s pseudorandom-number generator satisfies the clock generator limitation (claim 2), and its feedback loop that subtracts the offset from the ADC output meets the requirements of claims 4 and 5.

Ground B: Obviousness of Claims 7 and 8 over Jamal in view of Ferragina

  • Prior Art Relied Upon: Jamal and Ferragina (V. Ferragina et al., “Gain and offset mismatch calibration in multi-path sigma-delta modulators,” ISCAS ’03 Proceedings, 2003).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the system taught by Jamal. Claim 7 adds a "corrector" configured to "adjust the difference between the first and second offset signals." Petitioner argued that while Jamal corrects each channel's offset to zero individually, Ferragina explicitly teaches correcting offset mismatch in interleaved ADCs by adjusting the offsets of multiple paths to be equal to a reference path's offset. Ferragina’s averaging block calculates the difference between a path under calibration and a reference path, and the result is added to the calibrated path's output. This system was presented as the claimed "corrector."
    • Motivation to Combine: A POSITA would combine Ferragina’s offset equalization technique with Jamal’s offset correction system to achieve the predictable result of reducing spurious tones caused by offset mismatches between parallel channels. This was characterized as a simple substitution of one known offset correction goal (setting to zero) for another (setting to a common reference value) to solve a known problem.
    • Expectation of Success: The combination was asserted to be a predictable integration of known techniques to improve the performance of interleaved ADCs.

Ground C: Obviousness of Claim 12 over Elbornsson in view of Jamal

  • Prior Art Relied Upon: Elbornsson (J. Elbornsson et al., “Analysis of Mismatch Effects in Randomly Interleaved A/D Converter Systems,” Linköping University Report, Mar. 2003) and Jamal.

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Elbornsson taught the base system of claim 10 (from which claim 12 depends), including a plurality of converter circuits in a "Random interleaved ADC system" clocked by a "random select" block. Elbornsson also discloses an offset sensing and correction system using a digital moving average filter. To the extent Elbornsson does not explicitly teach implementing the system on an integrated circuit or a specific "sampling circuit," Petitioner argued Jamal supplies these elements. Claim 12 requires the sampling to be provided by a "sampling circuit clocked by said random clock to decorrelate the analog input signal." Petitioner contended that Jamal's "random chopping" circuit, which uses a pseudorandom signal to modulate the input, performs this function and would have been an obvious addition to Elbornsson's system.
    • Motivation to Combine: A POSITA would have been motivated to combine Jamal's random chopper-based offset calibration with Elbornsson's randomly interleaved ADC to improve performance. Jamal explicitly teaches that its chopping technique eliminates notches in the ADC output spectrum, enabling the conversion of signals with useful information at or near DC. Applying this known technique from Jamal to improve the known system of Elbornsson would yield the predictable result of a more robust ADC system.
    • Expectation of Success: Both references address similar technologies, and combining them represented the application of a known technique (Jamal's chopping) to improve a similar device (Elbornsson's ADC) in a predictable way.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 12 based on Eklund (Patent 6,392,575) in view of Jamal, which relied on a similar theory of combining a known randomly interleaved ADC system with Jamal's chopping and offset correction techniques.

6. Arguments Regarding Discretionary Denial

  • Petitioner argued that the Board should not exercise discretionary denial. Under the General Plastic factors, Petitioner asserted that this petition was not abusive as it challenges a unique set of claims not included in two prior-filed IPRs against the ’750 patent. The petition was filed promptly in response to Patent Owner’s unexpected assertion of these claims in parallel litigation Infringement Contentions.
  • Under the Fintiv factors, Petitioner argued against denial because the district court trial was scheduled more than 18 months after the petition filing date, meaning a Final Written Decision would likely issue well before trial. Petitioner also noted its intent to seek a stay upon institution, the limited investment in the parallel proceeding at the time of filing, and the fact that the IPRs challenge claims not asserted in the district court.

7. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-2, 4-8, and 12 of the ’750 patent as unpatentable.