Xilinx Inc v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2020-01567
• Patent #: 7,126,214
• Filed: September 4, 2020
• Petitioner(s): Xilinx, Inc.
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 1-6, 26-31

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’214 patent relates to a reconfigurable processor module formed by stacking thinned integrated circuit die elements, such as a microprocessor, memory, and a field-programmable gate array (FPGA). The patent describes interconnecting these stacked elements using contacts that traverse the thickness of the dies.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka - Claims 1-2, 4, 6, 26-27, 29, 31

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Zavracky taught the foundational concept of vertically stacking and interconnecting different types of integrated circuit functional elements, including programmable logic devices, memory, and microprocessors, using through-die "via holes." Chiricescu, which explicitly referenced Zavracky, taught a 3D FPGA with an integrated, stacked memory layer specifically to store configuration data and accelerate the FPGA reconfiguration process. Akasaka taught high-performance 3D ICs using "tens of thousands of via holes" distributed across the die surfaces to create dense, high-bandwidth interconnects that improve signal processing speed.
  • Motivation to Combine: A POSITA would combine Zavracky’s stacked architecture with Chiricescu’s use of stacked memory to solve the well-known problem of slow FPGA configuration times. Because Chiricescu built upon Zavracky's technology, this combination was presented as a predictable step. A POSITA would further incorporate Akasaka’s high-density, distributed via structure to increase bandwidth and processing speed, a known advantage for parallel processing applications like those described in Zavracky.
  • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involved applying known techniques (accelerated reconfiguration from Chiricescu, high-density interconnects from Akasaka) to a known platform (Zavracky's 3D stack) to achieve predictable performance improvements.

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Satoh - Claims 3 and 28

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Satoh to the primary combination. Petitioner argued that Satoh taught using an on-chip FPGA's variable logic circuit to generate a "specified test signal" (i.e., test stimulus) and supply it to co-located memory circuits to test their functionality. This directly mapped to claim limitations requiring contact points functional to provide a "test stimulus" from the FPGA to another integrated circuit element.
  • Motivation to Combine: Petitioner contended that a POSITA would have recognized that creating a complex 3D stack of multiple functional elements, as taught by the primary combination, inherently increased the risk of manufacturing defects and module failure. To improve yield and avoid the cost of "dead" chips, a POSITA would be motivated to incorporate testing. Satoh provided a known, efficient, and cost-effective method for using the existing on-stack FPGA for this purpose, thereby avoiding the expense and design complexity of a separate, dedicated testing chip.
  • Expectation of Success: The expectation of success was argued to be high because using an FPGA for testing circuitry was a well-known technique, and its application was not dependent on whether the target circuitry was in a 2D or 3D arrangement.

Ground 3: Obviousness over Zavracky, Chiricescu, Akasaka, and Alexander - Claims 5 and 30

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Alexander (a 1995 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Alexander to the primary combination. Petitioner asserted that Alexander taught building a powerful 3D FPGA by stacking multiple 2D FPGA dies and vertically interconnecting them. This teaching directly mapped to claim limitations that recite a third integrated circuit element that includes "another field programmable gate array."
  • Motivation to Combine: A POSITA seeking to build a high-performance system for parallel processing applications (a stated goal of Zavracky) would be motivated to enhance the base combination with additional processing capability. Alexander taught that stacking multiple FPGAs was a preferable method for such applications compared to slower general-purpose microprocessors or more expensive and inflexible custom hardware. Therefore, adding another FPGA layer from Alexander was a logical and motivated design choice.
  • Expectation of Success: Petitioner claimed a high expectation of success because stacking another FPGA element, as taught by Alexander, was structurally analogous to stacking the microprocessor and memory layers already taught in Zavracky. The combination represented a straightforward integration of a known component to enhance a known system for its intended purpose.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) and the Fintiv factors would be inappropriate. The petition noted that the scheduled trial date in the parallel district court litigation (May 23, 2022) was several months after the projected Final Written Decision from the Board (March 2022).
• Petitioner further strengthened its argument by offering a stipulation to not pursue in the district court any invalidity grounds that were instituted and decided in the IPR. It was also argued that denial under §325(d) was unwarranted because the asserted prior art combinations had not been considered by the USPTO during the original prosecution.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-6 and 26-31 of Patent 7,126,214 as unpatentable.