Xilinx Inc v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2020-01571
• Patent #: 6,781,226
• Filed: September 4, 2020
• Petitioner(s): Xilinx, Inc.
• Patent Owner(s): Jon M. Huppenthal
• Challenged Claims: 1-30

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’226 patent discloses a reconfigurable processor module created by stacking thinned integrated circuit die elements, such as a microprocessor, memory, and a field-programmable gate array (FPGA). The stacked die are interconnected using contacts that traverse the thickness of the die.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka - Claims 1-6 are obvious over Zavracky in view of Chiricescu and Akasaka.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Zavracky taught the foundational concept of a 3D processor module by vertically stacking and interconnecting different circuit elements, including programmable logic devices, microprocessors, and memory. Zavracky’s interconnects (“via holes”) could be placed anywhere on the die, not just the periphery. Chiricescu, which explicitly builds on Zavracky’s technology, disclosed using a 3D-layered FPGA with stacked on-chip memory to significantly improve FPGA reconfiguration time. Akasaka taught using tens of thousands of distributed through-die via holes to increase interconnection density, enabling parallel processing and higher operating speeds in 3D integrated circuits. The combination of these references allegedly taught every element of independent claim 1, including a processor module with stacked FPGA and microprocessor die elements electrically coupled to accelerate data processing.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Zavracky with Chiricescu because Chiricescu expressly used Zavracky's principles to solve the known problem of high FPGA configuration time. A POSITA would have been further motivated to incorporate Akasaka's high-density, distributed interconnects into the Zavracky/Chiricescu stack to predictably increase bandwidth and processing speed, benefits explicitly taught by Akasaka.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination involved applying known techniques (high-density interconnects, stacked memory for reconfiguration) to a known 3D architecture to achieve predictable improvements in performance.

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Satoh - Claims 7-12 are obvious over the combination of Ground 1 in view of Satoh.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground adds Satoh to address the limitations of independent claim 7, which requires the FPGA to be configured to provide test stimulus to the microprocessor during manufacture and prior to packaging. Petitioner asserted that Satoh taught a method for manufacturing a semiconductor integrated circuit wherein an FPGA is configured with a test circuit to generate test signals for an on-chip CPU (microprocessor). Satoh specified this testing occurs during manufacturing to improve yield by identifying faulty components before the final packaging step.
  • Motivation to Combine: A POSITA building the complex, multi-die stack taught by the primary combination would recognize the increased risk of module failure. To avoid the significant expense of packaging defective modules, a POSITA would have been motivated to implement in-situ testing during manufacture. Satoh provided a known and advantageous solution by using the already-present FPGA to test the co-stacked microprocessor, thus avoiding the need for separate testing hardware.
  • Expectation of Success: Success would be expected, as using an FPGA for testing was a known and routine application that was not dependent on the 2D or 3D structure of the device under test.

Ground 3: Obviousness over Zavracky, Chiricescu, Akasaka, and Trimberger - Claims 13-30 are obvious over the combination of Ground 1 in view of Trimberger.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Trimberger (a 1997 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground adds Trimberger to address the means-plus-function limitations of independent claims 13 and 22, which recite a "means for reconfiguring the programmable array within one clock cycle." Petitioner argued that Trimberger taught a time-multiplexed FPGA where the entire configuration could be changed in a single cycle. Trimberger achieved this using multiple on-chip memory planes and a wide configuration data port that could simultaneously update all bits in the logic and interconnect array from a selected memory plane, directly corresponding to the structure required by the claims.
  • Motivation to Combine: A POSITA would have been motivated to incorporate Trimberger’s teachings to solve the very problem Chiricescu identified as a "main bottleneck": high configuration time. For real-time applications, improving reconfiguration speed is critical. Trimberger provided a known and specific architecture for achieving ultra-fast, single-cycle reconfiguration, making it a natural and desirable improvement to the Zavracky/Chiricescu FPGA.
  • Expectation of Success: Combining a known method for rapid reconfiguration (Trimberger) with a 3D stacked FPGA architecture (Zavracky/Chiricescu) was a combination of known elements to achieve a predictable result.

4. Key Claim Construction Positions

• "means for reconfiguring the programmable array within one clock cycle" (claim 13) and "means for updating the plurality of configuration logic cells within one clock cycle" (claim 22): Petitioner argued these are means-plus-function terms governed by pre-AIA 35 U.S.C. § 112, ¶ 6. Petitioner identified two alternative structures disclosed in the ’226 patent corresponding to the claimed function:
  • Structure 1: "a wide configuration data port [used] to update the various logic cells through an associated configuration memory and buffer cell."
  • Structure 2: "a stacked FPGA die and memory die interconnected by a wide configuration data port using contact points distributed throughout the dies."
• Petitioner contended that the prior art combination for Ground 3, particularly Trimberger, disclosed structure identical or structurally equivalent to these constructions.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §325(d) was inappropriate because none of the asserted prior art references or combinations were considered during the patent’s prosecution, which involved no substantive rejections.
• Petitioner argued that denial under §314(a) based on General Plastic or Fintiv factors was unwarranted. Key arguments included:
  • The co-pending district court litigation was in a very early stage, with a trial date set for May 2022, well after the projected Final Written Decision in this IPR (March 2022).
  • The petitioner is distinct from another petitioner (Samsung) that previously challenged the patent, and this petition challenges a different set of claims.
  • The strength of the petition’s merits favored institution, as the claims had never been tested against prior art.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-30 of the ’226 patent as unpatentable.