PTAB

IPR2020-01599

Analog Devices Inc v. Xilinx Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method and Apparatus for Operating a Transceiver in Different Data Rates
  • Brief Description: The ’767 patent discloses a transceiver with a serializer designed to operate optimally within a narrow, high-speed range. To support slower communication protocols, a transmitter interface is placed between a data source and the serializer to repeat or "stretch" data bits, allowing the serializer to maintain its high operational data rate while the effective data rate is lowered.

3. Grounds for Unpatentability

Ground 1: Anticipation over Rambus - Claims 1-11 are anticipated by Rambus.

  • Prior Art Relied Upon: Rambus (Patent 7,190,754).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Rambus disclosed every limitation of the challenged claims. Rambus taught a "Selectable Data Rate Transmit Circuit" to support multiple output data rates without modifying high-speed clock circuitry, addressing the same problem as the ’767 patent. Independent claim 1’s transceiver with a two-state control signal was allegedly disclosed by Rambus’s circuit, which used a TDRSEL control signal to switch between a double data rate (DDR) mode and a single data rate (SDR) mode. The claimed "first interface" was mapped to Rambus's multiplexer circuitry (809, 811), which receives data from a data source (application logic 825) and delivers it to a serializer (803).
    • In the "first state" (SDR mode), Rambus’s interface performed "duplicated bit entry," replicating bits to effectively halve the data rate, which Petitioner argued anticipated the '767 patent’s "stretching" of data. In the "second state" (DDR mode), data passed through without replication. Petitioner asserted this directly mapped to claim 1, where the data rate from the source is lower than the serializer’s rate in the first state but the same in the second state. Dependent claims were allegedly met as Rambus also disclosed corresponding clock generation circuits, bit replication functionality, and a parallel receiver-side architecture performing the inverse operation.

Ground 2: Anticipation over Lucent - Claims 1, 6, and 10 are anticipated by Lucent.

  • Prior Art Relied Upon: Lucent (a September 2000 data sheet for the ORT8850 Field-Programmable System Chip).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Lucent, a publicly available data sheet, disclosed an embedded transceiver with a high-speed interface (HSI) macrocell (a SERDES) and a synchronous transport module (STM) macrocell. The STM macrocell included a "repeater" block that anticipated the claimed "first interface." To support slower protocols (e.g., STS-3 at 155 Mbits/s) on a fixed-rate serializer (622 Mbits/s), the repeater rearranged data so that "each bit is transmitted four or twelve times," thereby simulating a slower serial data rate. This bit repetition was argued to be the same as the "stretching" in the ’767 patent.
    • A control signal selected the mode of operation: STS-12 mode was a "pass-through" state (second state) where data was sent at the full rate, while STS-3 mode was a bit-repeating state (first state) where the effective data rate was lower. Petitioner argued this anticipated claim 1. For claims 6 and 10, Lucent’s corresponding "sampler" block was alleged to perform the inverse operation on the receiver side, sampling every Nth bit to discard the repeated bits, thus anticipating the claimed receiver interface and bit-removal limitations.

Ground 3: Obviousness over Lucent and Iowa - Claims 2-5, 7-9, and 11 are obvious over Lucent in view of Iowa.

  • Prior Art Relied Upon: Lucent (a September 2000 data sheet) and Iowa (Patent 5,982,309).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that while Lucent taught the core bit-repeating interface of claim 1, Iowa supplied the specific clock generation circuit limitations required by the dependent claims. Iowa disclosed a parallel-to-serial converter with a selectable bit-width mode and a clock generating circuit that adjusted the frequency of a loading clock in response to a control signal. This circuit could take a reference clock and output a clock at either the full frequency or half the frequency.
    • Motivation to Combine: A POSITA would combine Lucent and Iowa to achieve a common goal: enabling a fixed high-speed SERDES to support multiple data rates. Lucent provided the bit-repeating interface but was silent on clocking implementation details for the data source. Iowa provided a well-known, off-the-shelf solution for generating the necessary variable-rate clock signals from a master reference clock, as required to interface a data source with such a system. The combination was presented as a simple integration of a known clocking module (Iowa) with a known data-rate adaptation interface (Lucent).
    • Expectation of Success: Because both components performed well-known functions to achieve a common, predictable result, a POSITA would have had a reasonable expectation of success in combining them. The combination would result in a transceiver where Lucent's repeater duplicates data bits while Iowa's clock circuit, controlled by the same mode signal, generates a half-speed clock for the data source, directly teaching the limitations of claims 2, 3, 7, 8, and 9.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under §314(a) and the Fintiv factors. It was asserted that the co-pending district court litigation was before a judge who typically stays cases pending IPR. Furthermore, the trial was scheduled for a date after a Final Written Decision would issue in the IPR. Petitioner also noted that the IPR challenges claims that are not at issue in the parallel litigation, weighing against denial.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-11 of the ’767 patent as unpatentable.