PTAB

IPR2020-01606

Analog Devices Inc v. Xilinx Inc

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: RECEIVER TERMINATION NETWORK AND APPLICATION THEREOF
  • Brief Description: The ’590 patent discloses a receiver termination network for high-speed serial data signals. The network includes a DC matched termination circuit to suppress signal reflections and an AC coupled bias circuit to filter the data, which is then amplified and recovered.

3. Grounds for Unpatentability

Ground I: Claims 1, 7, and 15 are anticipated by IEEE 1149.6.

  • Prior Art Relied Upon: IEEE 1149.6-2003 (“IEEE 1149.6”) or IEEE 1149.6 Draft 2.3n (“Draft 2.3n”).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that IEEE 1149.6, a standard for testing advanced digital networks, discloses every element of the independent claims. Specifically, Figure 12 of IEEE 1149.6 was asserted to show a high-speed receiver with a termination network comprising a DC matched termination circuit (resistor RL) and an AC coupled bias circuit (capacitors and biasing resistors). This circuit provides a common mode reference (VBias), high-pass filters the data, and provides the filtered data to a receiver analog front-end (RX amp) for amplification. Petitioner further contended that IEEE 1149.6 discloses a data recovery module (capture and update flip-flops) that recovers data from the amplified signal. For dependent claim 7, Petitioner argued IEEE 1149.6 explicitly teaches matching the termination resistor RL to the characteristic impedance of the transmission line.

Ground II: Claims 1, 7, 8, and 15 are anticipated by HFAN-1.0.

  • Prior Art Relied Upon: HFAN-1.0 Rev. 0, “Introduction to LVDS, PECL, and CML,” a Maxim Integrated Products application note (“HFAN-1.0”).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Figure 16(a) of HFAN-1.0 discloses a circuit functionally identical to that claimed. The figure shows a receiver termination network for high-speed communication systems that includes a 100 Ω DC matched termination resistor and an AC coupled bias circuit. The AC coupled bias circuit was argued to include AC-coupling capacitors and a resistor network that provides a specified common-mode voltage to bias the receiver amplifier (an LVPECL receiver). This combination of capacitors and resistors acts as a high-pass filter. For the data recovery module, Petitioner argued that HFAN-1.0 teaches using the circuit with receivers like the MAX3675 chip, which contains a D flip-flop to recover data from the amplified signal. Dependent claim 8 was argued to be met because Figure 16(a) shows a bias impedance with resistance (4.3 kΩ) at least one order of magnitude greater than the termination resistor (100 Ω).

Ground III: Claims 2-4, 9-14, 16-18, and 21-22 are obvious over DS_ORT8850 in combination with IEEE 1149.6 or HFAN-1.0.

  • Prior Art Relied Upon: DS_ORT8850, a Lucent Technologies data sheet for a multi-gigabit transceiver (“DS_ORT8850”), in combination with either IEEE 1149.6 or HFAN-1.0.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that DS_ORT8850 discloses a multi-gigabit transceiver with receiver and transmit sections, meeting the preamble of independent claim 9. The receiver section in DS_ORT8850 includes a basic DC termination circuit. Petitioner argued a POSITA would have been motivated to modify the receiver in DS_ORT8850 by incorporating the more advanced AC coupled termination networks taught in either IEEE 1149.6 or HFAN-1.0. For the dependent claims, Petitioner argued that DS_ORT8850 discloses a "split-resistor" termination (two 50 Ω resistors in series), teaching the elements of claims 2, 10, and 16. It also discloses a center-tap pin, teaching the termination biasing pad of claims 3, 11, and 17.
    • Motivation to Combine: A POSITA would combine the references to improve the flexibility of the DS_ORT8850 transceiver, allowing it to be compatible with different logic families (e.g., LVPECL, CML) that have different common-mode voltage requirements. The AC coupling taught by IEEE 1149.6 and HFAN-1.0 explicitly addresses this problem by decoupling the receiver’s bias from the transmitter’s bias.
    • Expectation of Success: The combination involved applying a known solution (AC coupled termination) to a known problem (incompatibility between logic families), which would have been a straightforward implementation for a POSITA with a high expectation of success.
  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 6 and 20 based on combinations including Allen (“CMOS Analog Circuit Design”), which teaches a specific, efficient structure for fabricating capacitors on a chip.

4. Key Claim Construction Positions

  • "AC coupled": Petitioner proposed this term be construed as "coupling only the AC components of a signal from an input to an output of a circuit; the DC component of the signal is blocked." This construction was argued to be critical because the blocking of the DC component is a key function of the claimed AC coupled bias circuit.
  • "data recovery module...": Petitioner argued this term should be construed as a means-plus-function term under §112, para. 6. The claimed function is "to recover data from the amplified high-speed data." The corresponding structure disclosed in the ’590 patent's specification was identified as the "data detection circuit 110."

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §314(a) based on Fintiv factors would be inappropriate. The petition asserted that the co-pending district court litigation is before a judge who typically stays cases when a parallel IPR is instituted. Furthermore, the scheduled trial date was well after the deadline for a Final Written Decision in the IPR, minimizing concerns of duplicative efforts or inefficiency.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 6-18, and 20-22 of the ’590 patent as unpatentable.