Impinj Inc v. NXP BV

1. Case Identification

• Case #: IPR2020-01629
• Patent #: 7,374,097
• Filed: September 21, 2020
• Petitioner(s): Impinj, Inc.
• Patent Owner(s): NXP USA, Inc.
• Challenged Claims: 1-7

2. Patent Overview

• Title: Data Carrier for Storing Information Represented by an Information Voltage
• Brief Description: The ’097 patent describes a data carrier, such as an RFID tag, with an electrical circuit that generates its own supply voltage from a received signal. The technology aims to solve the problem of information voltage decay in capacitive storage by incorporating "voltage-raising means," such as a charge pump, to boost a control signal voltage before it is used to store information.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 4, 5, and 7 are Anticipated or Obvious over Vega

• Prior Art Relied Upon: Vega (Patent 6,147,605)
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Vega, which discloses RFID tags and circuits, anticipates or renders obvious all limitations of the challenged claims. For independent claims 1 and 4, Vega's RFID tag was asserted to be the claimed "data carrier" with an "electrical circuit" that receives a signal wirelessly and generates a supply voltage (Vcc) via a rectifier. Vega's EEPROM memory (220) was identified as the "storage means" that stores information capacitively, represented by a voltage value. Petitioner contended that Vega's charge pump (223), which receives the supply voltage Vcc as a control signal and raises it to a higher programming voltage (Vpp), directly meets the "voltage-raising means" limitation. For the dependent claims, Vega's charge pump (223) was argued to be the specific implementation required by claims 2 and 5, and its integrated circuit (116) was asserted to meet the limitation of claim 7.
  • Motivation to Combine (for §103 grounds): The primary argument was anticipation under 35 U.S.C. §102. In the alternative for obviousness, Petitioner argued that for claims 2 and 5, which require raising the control signal voltage by the value of the supply voltage, Vega’s disclosure of a multi-stage, variable charge pump made such a configuration obvious. A person of ordinary skill in the art (POSITA) would understand that the number of stages could be adjusted based on voltage requirements. A POSITA would combine a first stage and a final stage, omitting intermediate stages, to achieve an output of twice the supply voltage, thereby raising the voltage by the value of the supply voltage itself.
  • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success in modifying the number of stages in Vega's charge pump, as it was a well-known circuit with predictable behavior based on its configuration.

Ground 2: Claims 3 and 6 are Obvious over Vega

• Prior Art Relied Upon: Vega (Patent 6,147,605)
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that building on the disclosures that render claims 1 and 4 obvious, Vega also renders obvious the addition of a "voltage-limiting means" as required by claims 3 and 6. Vega discloses, in an alternative embodiment (Figs. 16-17), the use of voltage regulators (1000, 1002), implemented as Zener diodes, to limit DC voltage. This regulator was asserted to be the claimed "voltage-limiting means."
  • Motivation to Combine (for §103 grounds): A POSITA would combine the charge pump circuit of Vega's primary embodiment (Fig. 3) with the voltage-limiting Zener diode from its alternative embodiment (Fig. 17). The motivation would be to protect sensitive downstream components, such as the memory (220), from potential voltage spikes at the output of the charge pump. This is a common and predictable design choice to improve circuit reliability and prevent damage.
  • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success in adding a well-known voltage-limiting component, like a Zener diode, to the output of a well-known charge pump circuit to achieve the predictable result of voltage regulation.

4. Key Claim Construction Positions

Petitioner contended that several claim terms should be construed as means-plus-function limitations under 35 U.S.C. §112(f), linking them to specific structures in the ’097 patent specification.

• "storage means that are arranged to store information capacitively": Petitioner asserted the recited function is storing information capacitively, and the corresponding structure disclosed in the ’097 patent is a storage capacitor (5A).
• "information-voltage generating means": Petitioner asserted the recited functions are receiving a control signal and generating an information voltage using that signal. The corresponding structure was identified as the components within Box 6 of Figures 1 and 2 of the ’097 patent.
• "voltage-raising means that are... arranged to raise the voltage value of the control signal": Petitioner argued the recited function is raising the control signal's voltage value. The corresponding structure was identified as a charge pump (10), which includes a capacitor (11) and switches (12, 13).
• "voltage-limiting means that are... arranged to limit the raising of the voltage value": Petitioner asserted the recited function is limiting the raising of the control signal's voltage. The corresponding structure was identified as a diode configuration (component 9 in Fig. 2).

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-7 of the ’097 patent as unpatentable.