PTAB

IPR2020-01630

Impinj Inc v. NXP BV

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Wafer with Process Control Modules
  • Brief Description: The ’523 patent relates to the design of semiconductor wafers and the arrangement of test structures, known as process control modules (PCMs). The disclosed invention involves placing PCMs on a wafer by replacing at least one functional integrated circuit (chip) within an exposure field, aiming to optimize process monitoring without significant loss of usable wafer area.

3. Grounds for Unpatentability

Ground 1: Claims 1-4 are anticipated by or obvious over Yamaguchi.

  • Prior Art Relied Upon: Yamaguchi (Patent 6,492,189).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yamaguchi discloses every limitation of claims 1-4. Yamaguchi teaches a method for arranging test modules on a wafer, explicitly noting the limitations of placing them in scribe lines and the benefit of replacing chip areas. It describes creating exposure fields containing both device chips and “test element groups” (TEGs) or alignment markers, which are functionally equivalent to the claimed PCMs. Petitioner asserted that Yamaguchi shows these TEGs and alignment marks taking the place of “one to several semiconductor chips.” For dependent claims 2-4, Petitioner pointed to Yamaguchi’s disclosure of placing an alignment marker in the same location (e.g., bottom-right corner) of every exposure field, arguing this meets the limitations of having a PCM in at least 25% of fields (claim 2), in each field (claim 3), at equal distances due to the use of fixed-pitch stepping (claim 2), and at the same location in each respective field (claim 4).
    • Motivation to Combine (for §103 grounds): This ground was primarily asserted as anticipation. In the alternative, for obviousness, the motivation would be inherent in Yamaguchi's own teachings to solve the known problem of efficiently placing test structures on a wafer.
    • Expectation of Success (for §103 grounds): Petitioner contended success would be expected because Yamaguchi explicitly describes the structures and methods for placing PCMs in place of chips.

Ground 2: Claims 1-4 are anticipated by or obvious over Satya.

  • Prior Art Relied Upon: Satya (Patent 6,633,174).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Satya, which is directed to semiconductor defect test structures, discloses the claimed invention. Satya’s Figure 4b illustrates a “die array” (an exposure field) with an orderly, grid-like layout of both “product dies” (chips) and “test dies” (PCMs), where the test dies replace product dies. Petitioner asserted that Satya teaches that this reticle pattern can be stepped across an entire wafer. This standard manufacturing process would inherently create a wafer meeting the limitations of claim 1. For the dependent claims, Petitioner argued that stepping the reticle shown in Figure 4b across the wafer would result in a PCM being present in 100% of the exposure fields, thereby satisfying the “at least 25%” limitation of claim 2 and the “in each exposure field” limitation of claim 3. The orderly layout and repetitive stepping process would also ensure the PCMs are situated at equal distances (claim 2) and at the same relative locations within each field (claim 4).
    • Motivation to Combine (for §103 grounds): Asserted as anticipation, with an alternative obviousness argument. The motivation is to use Satya's disclosed test die arrangement for its intended purpose of process control across a wafer.
    • Expectation of Success (for §103 grounds): Petitioner argued success was expected because Satya explicitly teaches creating wafers with these test structures and describes their orderly arrangement as a design choice.

Ground 3: Claims 1-4 are obvious over Yamaguchi in view of Satya.

  • Prior Art Relied Upon: Yamaguchi (Patent 6,492,189) and Satya (Patent 6,633,174).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that to the extent any claim element is not fully disclosed by Yamaguchi or Satya alone, the combination of their teachings renders claims 1-4 obvious. Both references address the same problem of integrating test structures onto semiconductor wafers.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) seeking to optimize the placement of test structures would combine the teachings of Yamaguchi and Satya. Petitioner argued a POSITA would look to Yamaguchi’s disclosure of replacing chips with TEGs and alignment marks and be motivated to implement the orderly, grid-like arrangement of test dies shown in Satya to achieve predictable and uniform testing coverage. The combination reinforces the teachings of each reference, making the claimed configuration a predictable solution.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in combining the references because both operate within the same well-established field of semiconductor lithography and address analogous problems with compatible solutions.

4. Key Claim Construction Positions

  • "Each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2)": Petitioner argued this phrase does not require that every exposure field on the wafer contains the exact same number of chips. This construction is crucial because an exposure field containing a PCM that replaces a chip would necessarily have a different (fewer) number of chips than an exposure field without a PCM. Petitioner contended the patent’s own disclosure supports this view, as it describes scenarios where PCMs are present in only 25% or 50% of the exposure fields.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4 of Patent 6,680,523 as unpatentable.