PTAB

IPR2020-01669

Taiwan Semiconductor Mfg Co Ltd v. Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung Ev

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Method for Producing a Three-Dimensional Integrated Circuit
  • Brief Description: The ’391 patent discloses methods for producing three-dimensional integrated circuits by stacking semiconductor substrates. The purported novelty centers on connecting two substrates such that the electrical and mechanical connection is established exclusively via metallic "lands," without requiring a separate adhesive or underfill layer.

3. Grounds for Unpatentability

Ground 1: Obviousness over Gaynes - Claims 1-4, 6, 8, 12-13 are obvious over Gaynes.

  • Prior Art Relied Upon: Gaynes (Patent 6,002,177).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Gaynes teaches every limitation of the independent claims. Gaynes discloses a method for stacking semiconductor chips using conductive through-vias and connecting them with metallic lands. The connections are formed using a transient liquid phase (TLP) bonding process (e.g., with lead and tin), which creates a strong eutectic alloy. Petitioner contended this TLP connection provides both the required electrical conductivity and mechanical stability, thereby satisfying the "exclusivity" limitation without needing a separate adhesive layer. Gaynes also discloses the dependent claim features, such as using doped semiconductor material for contact areas (claim 2) and arranging metallization planes on the main surface (claims 3-4).
    • Motivation to Combine (for 35 U.S.C. §103 grounds): Not applicable as this ground relies on a single reference.

Ground 2: Obviousness over Gaynes and Gurtler - Claims 1-4, 6, 8, 12-13 are obvious over Gaynes in view of Gurtler.

  • Prior Art Relied Upon: Gaynes (Patent 6,002,177) and Gurtler (Patent 5,424,245).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that Gaynes teaches all claim limitations except for the explicit requirement that the via holes are "electrically insulated from said first semiconductor substrate." While Petitioner argued this is implicit in Gaynes for an operable device, Gurtler was introduced for its express teaching of this feature. Gurtler specifically discloses forming a dielectric layer via thermal oxidation or chemical vapor deposition (CVD) to provide electrical isolation for through-substrate vias.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Gurtler's insulation method with Gaynes's chip-stacking architecture to solve the well-known problem of preventing short circuits and current leakage between conductive vias and the semiconductor substrate. Both references are in the same field of vertical interconnection, making the combination logical.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as the thermal oxidation and CVD processes taught by Gurtler are standard, predictable semiconductor manufacturing techniques.

Ground 3: Obviousness over Gaynes and Bertin - Claim 7 is obvious over Gaynes in view of Bertin.

  • Prior Art Relied Upon: Gaynes (Patent 6,002,177) and Bertin (Patent 5,270,261).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground addressed dependent claim 7, which adds the limitation of connecting the first substrate to an auxiliary substrate and then thinning the first substrate from the opposite side. Petitioner argued that Bertin discloses this exact process. Bertin teaches flipping and bonding an integrated circuit chip to a carrier (an auxiliary substrate) and then etching the original substrate to thin it, exposing metallized trenches.
    • Motivation to Combine (for §103 grounds): A POSITA, seeking to implement the high-density stacking taught by Gaynes, would be motivated to use thinner substrates to improve performance and decrease interconnect length. Bertin provides a known and enabling method for achieving this substrate thinning in the context of multi-chip packages, making it a logical reference for a POSITA to consult and apply to the Gaynes system.
    • Expectation of Success (for §103 grounds): Success would be expected because Bertin teaches a well-defined method for forming conductive vias and thinning substrates in a multi-chip stack, providing predictable results.

  • Additional Grounds: Petitioner asserted additional obviousness challenges against claim 11, introducing EP366 to teach that not all connection lands need to be electrically active, allowing for "dummy lands" to provide mechanical support and improve thermal dissipation without affecting electrical characteristics.

4. Key Claim Construction Positions

  • "component structures including [] contact areas": Petitioner argued this term should be given its plain meaning consistent with the specification, which describes components like transistors and metallization planes. Petitioner contended this construction is necessary to counter a litigation position by the Patent Owner’s licensee that improperly broadens the term to include portions of an interposer.
  • "exclusively via the first and the second lands": Petitioner argued this "exclusivity" limitation means that the lands are the sole source of both electrical and mechanical connection, precluding any additional material like underfill or epoxy. This position was based on the patent's specification distinguishing prior art for using separate adhesive layers and the patent’s prosecution history where the applicant added this term to overcome prior art.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, stating that the petition presents an overwhelmingly strong case of unpatentability, particularly because European and Japanese examiners found the key "exclusivity" limitation to be well-known during prosecution of foreign counterparts. Other arguments included: the Patent Owner is not a party to the parallel district court litigation (only its licensee is); the IPR challenges 11 claims while the litigation asserts only claim 1; the trial date is tentative; and Petitioner stipulated it would not pursue the same invalidity grounds in district court if the IPR is instituted.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 6-8, and 11-13 of Patent 6,548,391 as unpatentable.