Micron Technology Inc v. Flash Control LLC

1. Case Identification

• Case #: IPR2020-01709
• Patent #: 9,257,184
• Filed: September 29, 2020
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Flash-Control, LLC
• Challenged Claims: 1-6 and 8-16

2. Patent Overview

• Title: Nonvolatile Memory Systems With Embedded Fast Read and Write Memories
• Brief Description: The ’184 patent describes a memory system that couples a nonvolatile memory (e.g., flash memory) with a volatile random access memory (RAM). The system is configured to transfer data from the nonvolatile memory to the volatile RAM, where it can be modified with granular access (at the bit or byte level) and then written back to the nonvolatile memory at a new physical location corresponding to the original logical address.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lee - Claims 1-3 and 9-16 are obvious over Lee and the knowledge of a POSA.

• Prior Art Relied Upon: Lee (Application # 2006/0053246).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Lee, a single reference, disclosed every limitation of the challenged claims. Lee described a cellular phone system with nonvolatile flash memory and volatile SDRAM. It taught downloading data (e.g., user data, book-keeping records) from the flash memory to the SDRAM, where it could be accessed and modified. Petitioner contended Lee’s disclosure of byte-level access and a burst mode of a single word met the "any portion" limitation of claim 1. Crucially, Lee was argued to disclose writing the modified data from the SDRAM back to the nonvolatile memory at a different physical location while maintaining the same logical address, a process known as wear leveling.
  • Motivation to Combine (for §103 grounds): As this ground relied on a single reference, Petitioner argued all elements were present in Lee's integrated system.
  • Expectation of Success (for §103 grounds): A POSA would have an expectation of success as Lee described a complete, functioning memory system.

Ground 2: Obviousness over Tsunoda and Kolokowsky - Claims 1-3, 5-6, 9, and 11-16 are obvious over Tsunoda in view of Kolokowsky.

• Prior Art Relied Upon: Tsunoda (Application # 2003/0028733) and Kolokowsky (Patent 7,853,749).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Tsunoda taught a memory apparatus with flash memory and SDRAM, where user data is copied to the SDRAM for modification and then written back to the flash memory. Tsunoda disclosed using logical addresses for the flash memory but did not explicitly state that modified data is written to a new physical location. Petitioner argued that Kolokowsky supplied this missing element by teaching a conventional wear-leveling technique where, upon a write command, data is written to a new, unallocated physical block, and the logical address is re-mapped to that new physical location.
  • Motivation to Combine (for §103 grounds): A POSA would combine Tsunoda with Kolokowsky's wear-leveling technique for well-understood benefits. These included extending the operational lifespan of Tsunoda's flash memory and improving write performance by writing to pre-erased blocks, avoiding the delay of erasing a block before rewriting.
  • Expectation of Success (for §103 grounds): A POSA would have a high expectation of success because Tsunoda’s use of logical addressing provided the necessary framework for implementing the conventional and well-known wear-leveling technique taught by Kolokowsky.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on substituting known memory technologies into the primary combinations. These included using Lee in view of Li (phase change memory) for claim 4; Lee in view of Miura (SRAM) for claim 8; Tsunoda/Kolokowsky in view of Li for claim 4; and Tsunoda/Kolokowsky in view of Miura for claim 8.

4. Key Claim Construction Positions

• "any portion": Petitioner argued this term, used in claim 1 for accessing and modifying data in the volatile memory, should be construed to mean access at the "addressable bit and/or a byte level." This construction was supported by the patent's file history, where the applicant distinguished prior art by emphasizing the invention's ability to provide granular access without needing to extract the entire contents of a page buffer.
• "on the fly": For claim 15, Petitioner proposed that "on the fly" has its well-understood meaning to a POSA: "doing a task or process as needed without suspending or disturbing normal operations." This construction was argued to be met by Lee's wear-leveling process, which occurs as a normal part of a write operation.

6. Arguments Regarding Discretionary Denial

• §325(d) - Same or Substantially the Same Prior Art: Petitioner argued that discretionary denial would be inappropriate because the primary prior art references, Lee and Tsunoda, were not before the examiner during the original prosecution. It was asserted that these references disclose the very features the applicant used to argue for patentability, making them highly material.
• §314(a) - Fintiv Factors: Petitioner preemptively argued against discretionary denial under Fintiv. It was noted that the co-pending district court litigation against the Petitioner had been stayed and that no trial date was set, suggesting that an IPR would be an efficient resolution and would not be duplicative of imminent court proceedings.

7. Relief Requested

• Petitioner requested institution of an inter partes review (IPR) and cancellation of claims 1-6 and 8-16 of the ’184 patent as unpatentable.