Micron Technology Inc v. Flash Control LLC

1. Case Identification

• Case #: IPR2020-01710
• Patent #: 9,792,219
• Filed: September 29, 2020
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Flash-Control, LLC
• Challenged Claims: 1-5, 7-13

2. Patent Overview

• Title: Nonvolatile Memory Systems with Embedded Fast Read and Write Memories
• Brief Description: The ’219 patent discloses a memory system architecture that couples a nonvolatile memory (e.g., Flash) with a volatile random access memory (e.g., DRAM). The system is designed to improve performance by transferring data from the nonvolatile memory to the volatile memory, allowing for granular access to "any portion" of the data, and then writing modified data back to the nonvolatile memory at a different physical location corresponding to the same logical address.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 and 8-13 are obvious over Lee.

• Prior Art Relied Upon: Lee (Application # 2006/0053246).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Lee, which discloses a cellular phone memory system, teaches all limitations of the challenged claims. Lee describes a system comprising a nonvolatile Flash memory and a volatile SDRAM. Data from the Flash memory, including user data and book-keeping records, is transferred to the SDRAM. Petitioner contended that Lee’s disclosure of standard SDRAM functionality inherently includes the capability for granular, byte-level access, thus satisfying the "any portion" limitation of claim 1. Crucially, Petitioner asserted Lee discloses a wear-leveling process where, upon writing data back to the Flash memory, it is written to a new physical address while the logical address is remapped, meeting the limitation of writing to a "different physical location with the same associated address."
  • Motivation to Combine (for §103 grounds): While this is a single-reference ground, Petitioner argued a person of ordinary skill in the art (POSA) would have understood that standard SDRAM protocols supported byte-level access. Lee provided the motivation for granular access by stating that processors "typically need random-access on a byte or word level."
  • Expectation of Success: A POSA would have a high expectation of success as implementing granular access and wear-leveling were conventional techniques for the memory types disclosed in Lee.

Ground 2: Claims 1-2, 4-5, 8, and 10-13 are obvious over Tsunoda in view of Kolokowsky.

• Prior Art Relied Upon: Tsunoda (Application # 2003/0028733) and Kolokowsky (Patent 7,853,749).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Tsunoda discloses a memory apparatus with Flash memory and SDRAM that meets most claim limitations. Tsunoda teaches copying user data from Flash to SDRAM upon power-up, allowing a host to access the data from the faster SDRAM. Petitioner argued that Tsunoda, like Lee, discloses the necessary components and the ability for granular, byte-level access to the SDRAM. However, Tsunoda does not explicitly teach writing modified data back to a different physical location in the Flash memory. Petitioner contended that Kolokowsky remedies this deficiency by teaching a conventional wear-leveling technique where data is written to unallocated or newly erased blocks to preserve the life of the Flash memory.
  • Motivation to Combine: A POSA would combine Kolokowsky's wear-leveling technique with Tsunoda’s system for the well-known benefit of extending the operational lifespan of the flash memory device. Tsunoda’s disclosure of logical addressing for its flash device provides the necessary framework for implementing Kolokowsky’s re-mapping of logical-to-physical addresses, which is the foundation of wear-leveling.
  • Expectation of Success: A POSA would have a high expectation of success in this combination because wear-leveling was a well-known, advantageous, and conventional technique for flash memory systems that used logical-to-physical address mapping, like the system in Tsunoda.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Lee with Li (Patent 7,254,059) for phase change memory (claim 3) and with Miura (Application # 2006/0041711) for SRAM (claim 7). Similar combinations were asserted against the Tsunoda/Kolokowsky combination.

4. Key Claim Construction Positions

• "any portion": Petitioner argued this term should be construed to mean access "down to the addressable bit and/or byte level." This construction was based on the prosecution history of a parent patent, where the applicant distinguished prior art by arguing the invention allows modification of data in the volatile memory (page buffer) without requiring the entire buffer's contents to be extracted. Petitioner asserted this implies granular access not present in the prior art of record.
• "on the fly": Petitioner proposed this term means "doing a task or process as needed without suspending or disturbing normal operations," adopting a construction from a PTAB decision in a related case. Petitioner argued that wear-leveling, which occurs as part of a normal write operation, satisfies this limitation.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §325(d) because the primary prior art references, Lee and Tsunoda, were not before the examiner during prosecution. Petitioner emphasized that these references disclose the very feature—granular modification of data in a volatile buffer—that the applicant relied upon to overcome prior art rejections.
• Petitioner also argued against discretionary denial under Fintiv, stating that the co-pending district court litigation had been stayed and no trial date was set, meaning the IPR would be a more efficient resolution.

6. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1-5 and 7-13 of the ’219 patent as unpatentable.