Impinj Inc v. NXP BV

1. Case Identification

• Case #: IPR2021-00001
• Patent #: 6,819,092
• Filed: October 5, 2020
• Petitioner(s): Impinj, Inc.
• Patent Owner(s): NXP BV.
• Challenged Claims: 1-4

2. Patent Overview

• Title: Digitally Switchable Current Source
• Brief Description: The ’092 patent discloses a digitally switchable current source circuit designed to prevent current spikes during the switching transitions of transistors. The described circuit utilizes multiple parallel branches, where each branch contains a pair of switching transistors arranged in series with a current source transistor to maintain a constant, uninterrupted current flow.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Tamura - Claims 1-4 are anticipated or obvious over Tamura.

• Prior Art Relied Upon: Tamura (Patent 6,247,138).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Tamura anticipated claims 1-3 and rendered all challenged claims (1-4) obvious under 35 U.S.C. §102 and §103. Tamura’s Figure 82 was alleged to disclose a bias signal generating circuit with a nearly identical architecture to that claimed in the ’092 patent. Specifically, Tamura taught a circuit with multiple parallel branches, each containing a pair of pMOS switching transistors (4487, 4488) arranged in series with a current source transistor (4486). Petitioner asserted this structure met the limitations of independent claim 1. Tamura’s use of an inverter (4489) to apply a digital control signal in an inverted form to one of the switching transistors was argued to meet the limitation of claim 2. Furthermore, Tamura’s disclosure that the outputs terminate in parallel current paths controlled by load transistors (44831, 44832) allegedly met the limitations of claim 3.
  • Motivation to Combine (for §103 grounds): For claim 4, which added a phase-locked loop (PLL) circuit, Petitioner argued a person of ordinary skill in the art (POSITA) would be motivated to use the current source of Tamura's Figure 82 within the PLL circuit disclosed elsewhere in Tamura (Figure 64). The motivation arose from predictable design improvements; using the simpler current source from Figure 82 would save space on an integrated circuit and consume less power compared to the more complex converter (135) shown in Tamura’s PLL diagram, while achieving the same intended function.
  • Expectation of Success: A POSITA would have had a high expectation of success as the modification involved substituting one known type of digitally-controlled current source for another within the same reference’s disclosed PLL system.

Ground 2: Anticipation by Brown - Claims 1-4 are anticipated by Brown.

• Prior Art Relied Upon: Brown (Patent 5,121,085).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Brown anticipated all challenged claims under §102. Brown disclosed a "switched current source" for use in a PLL that embodied all claim limitations. Brown’s Figure 3A showed a circuit with two parallel branches. One branch contained switching transistors Q3 and Q4 in series with current source transistors Q1 and Q2, while the second parallel branch contained switching transistors Q7 and Q8 in series with current source transistors Q5 and Q6. This configuration was argued to meet the structural limitations of claim 1. Brown’s use of a "complementary signal CHG" to control one transistor in each switching pair allegedly met the inverted signal limitation of claim 2. The termination of the switching transistor outputs into a path to be controlled (capacitor C1) was argued to meet the limitation of claim 3. Finally, because Brown’s entire switched current source was explicitly disclosed for use in a PLL with a voltage-controlled oscillator (VCO), Petitioner asserted that Brown also anticipated claim 4.

Ground 3: Obviousness over Tamura in view of Smith - Claims 1-4 are obvious over Tamura combined with Smith.

• Prior Art Relied Upon: Tamura (Patent 6,247,138) and Smith (Patent 5,402,358).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground was presented as an alternative argument contingent on a different claim construction, wherein the claims require "at least two current source transistors" to be arranged in parallel with each other before being placed in series with the switching transistors. Petitioner argued that while Tamura disclosed single current source transistors in each branch, Smith taught the well-known technique of "tiling" multiple smaller transistors in parallel to create a larger, more space-efficient transistor with greater current capacity.
  • Motivation to Combine: A POSITA would combine Smith’s tiling technique with Tamura’s circuit for predictable reasons of design optimization. To achieve a desired current output for Tamura’s current source transistors (4486), a POSITA would have been motivated to replace each single transistor with multiple, parallel-connected transistors as taught by Smith. This modification would achieve the required current capacity while minimizing the surface area on the integrated circuit, a standard design consideration.
  • Expectation of Success: The combination involved applying a known technique (parallel transistor tiling) to a known circuit element (a current source transistor) to achieve a predictable improvement in performance and efficiency, leading to a high expectation of success.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on Tamura combined with general knowledge and Brown combined with general knowledge, which relied on similar logic regarding the well-known principles of arranging current sources in parallel.

4. Key Claim Construction Positions

• Petitioner dedicated significant argument to construing the phrase: “two switching transistors . . . arranged in series with at least two current source transistors . . . are parallel arranged in a branch” (claims 1 and 4).
• Petitioner argued that based on the patent’s sole embodiment (Figure 1) and its prosecution history, a POSITA would interpret this language to mean a circuit having at least two parallel branches, where each branch contains a set of two switching transistors arranged in series with a current source transistor. This construction underpins Petitioner's primary anticipation arguments based on Tamura and Brown.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-4 of the ’092 patent as unpatentable.