Impinj Inc v. NXP BV

1. Case Identification

• Case #: IPR2021-00003
• Patent #: 7,538,444
• Filed: October 5, 2020
• Petitioner(s): Impinj, Inc.
• Patent Owner(s): NXP BV.
• Challenged Claims: 1-6

2. Patent Overview

• Title: Wafer with Optical Control Modules in Exposure Fields
• Brief Description: The ’444 patent discloses a semiconductor wafer layout designed to maximize the usable surface area for integrated circuits (ICs). The invention places optical control modules (OCMs), or alignment marks, in the corners of an exposure field by replacing a preset number of IC-containing lattice fields (dies), rather than placing them in the wider dicing paths (scribe lines) between the fields.

3. Grounds for Unpatentability

Ground 1: Claims 1-6 are obvious over Jeong in view of Yamaguchi.

• Prior Art Relied Upon: Jeong (Patent 5,733,690) and Yamaguchi (Patent 6,492,189).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Jeong taught the fundamental layout of a semiconductor wafer, including exposure fields with lattice fields containing ICs, separated by perpendicular dicing paths. Crucially, Jeong disclosed placing alignment marks at the four corners of a rectangular reticle to improve alignment accuracy, but taught placing them within the scribe lines. Yamaguchi addressed the problem of wasted wafer space caused by wide scribe lines needed to accommodate such marks. Yamaguchi explicitly taught that to enable narrower scribe lines, alignment marks and other test patterns should be moved out of the scribe lines and placed within the exposure field by replacing one or more semiconductor chips (i.e., lattice fields).
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Jeong’s teaching of placing alignment marks in the four corners of an exposure field for superior alignment with Yamaguchi’s teaching of replacing die with those marks. The motivation was to gain the alignment benefits taught by Jeong while simultaneously achieving the significant economic benefit of maximizing wafer real estate by narrowing the dicing paths, as explicitly taught by Yamaguchi.
  • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved applying a known space-saving strategy (Yamaguchi) to a known alignment mark configuration (Jeong). This was a predictable design choice, not an inventive leap.

Ground 2: Claims 1-6 are obvious over Chiang in view of Yamaguchi.

• Prior Art Relied Upon: Chiang (Patent 6,074,786) and Yamaguchi (Patent 6,492,189).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Chiang, like Jeong, disclosed placing alignment marks proximate to the corners of a rectangular reticle to solve alignment issues. While Chiang did not specify whether the marks were in the scribe lines or the device field, Petitioner contended a POSITA would understand them to be in the device field. Yamaguchi again provided the missing element: the explicit teaching of replacing lattice fields with alignment marks to allow for narrower scribe lines. Dependent claim 3, which requires four control module fields in the corners of a rectangular exposure field, was argued to be directly taught by Chiang.
  • Motivation to Combine: The motivation was identical to Ground 1. A POSITA seeking to implement the corner alignment marks of Chiang would be motivated by Yamaguchi’s clear disclosure to place those marks in the device area, replacing die. This would optimize the wafer layout for a higher chip yield, a primary concern in semiconductor manufacturing.
  • Expectation of Success: The combination of Chiang’s alignment mark placement with Yamaguchi’s space-optimization technique was a straightforward application of known principles to achieve a predictable improvement in manufacturing efficiency.

Ground 3: Claims 1-6 are obvious over Matsuura in view of Yamaguchi.

• Prior Art Relied Upon: Matsuura (Patent 6,084,678) and Yamaguchi (Patent 6,492,189).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Matsuura went a step further than Jeong by explicitly disclosing placing alignment marks in the four corners of an exposure field within the device/chip area, not in the scribe lines. Matsuura taught placing marks in an "area corresponding to selected ones of the chips." However, Matsuura did not specify that these marks must replace a die. Yamaguchi provided the rationale for this final step, teaching that as ICs and dies become smaller, it is advantageous to have alignment marks replace an entire die rather than share space within a larger one. This allows for narrower scribe lines. Claim 4, which requires each control module field to replace "one lattice field only," was argued to be a direct and obvious implementation of Yamaguchi’s teaching applied to Matsuura.
  • Motivation to Combine: A POSITA starting with Matsuura’s design of corner alignment marks within the chip area would have been motivated by Yamaguchi to refine that design. Specifically, as chip dimensions shrank over time, the POSITA would have been motivated to dedicate entire, small lattice fields to the alignment marks, as taught by Yamaguchi, to maximize the number of ICs on the wafer.
  • Expectation of Success: Modifying Matsuura’s design according to Yamaguchi’s teachings represented a predictable design evolution. A POSITA would expect that replacing a single small die with an alignment mark would successfully implement the alignment function while maximizing usable wafer area.

4. Key Claim Construction Positions

• "Exposure Field": Petitioner asserted this term is used interchangeably in the art with "reticle," "field," "shot," and "die array."
• "Lattice Field": Petitioner asserted this term is synonymous with a "die," which is the small block on the wafer where an IC is formed, with boundaries defined by the dicing paths.
• "Optical Control Modules" (OCMs): Petitioner asserted this term is synonymous with, or at least includes, an "alignment mark," used to align reticles and avoid overlay errors during the photolithography process.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-6 of the ’444 patent as unpatentable under 35 U.S.C. §103.