PTAB

IPR2021-00019

NVIDIA Corp v. Advanced Cluster Systems Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Computer Cluster System for Parallel Processing
  • Brief Description: The ’768 patent describes a computer cluster system for parallelizing mathematical computations. The system uses a plurality of nodes, each configured with a "kernel module" (e.g., Maple or Mathematica) and a "cluster node module" to enable peer-to-peer communication, allegedly improving upon prior art grid computing systems that lacked such inter-node communication capabilities.

3. Grounds for Unpatentability

Ground 1: Obviousness over Distributed Maple and Multi-Core Processor Art - Claims 1, 4-10, 18-22, 24-25, 30-31, and 33-34 are obvious over a combination of references.

  • Prior Art Relied Upon: Schreiner1 (“Distributed Maple: parallel computer algebra in networked environments,” a 2003 journal article), Schreiner2 (“Distributed Maple – User and Reference Manual (V 1.1.12),” a 2001 manual), Schreiner3 (“Task Logging, Rescheduling and Peer Checking in Distributed Maple,” a 2002 paper), Distributed Maple Code (source code for the Distributed Maple project), Maple Guide (“Maple V Learning Guide,” a 1998 guide), SPARC IV Article (“SUN Debuts UltraSPARC IV,” an Oct. 2003 article), and AMD Article (“AMD to Unveil Dual-Core PC Chips,” a May 2005 article).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the collection of references describing the "Distributed Maple" project (Schreiner1, Schreiner2, Schreiner3, and the Code), supplemented by the Maple Guide, teaches all core elements of independent claim 1. Schreiner1 disclosed a "computer cluster" of nodes capable of running on "heterogeneous clusters" and "shared-memory multiprocessors." Each node ran a Maple "single-node kernel" for evaluating mathematical expressions, and the cluster was initiated by a user command (dist[initialize]). The system’s dist.Scheduler and dist.maple software components provided a mechanism for peer-to-peer communication, explicitly described as allowing nodes to establish "direct connection[s] for message transfers." The "first node" (root) in the Distributed Maple system had a user interface (a standard Maple frontend) and was configured to distribute task calls to other nodes. The addition of a "plurality of processing cores" was argued to be an obvious modification, as the SPARC IV and AMD articles demonstrated that multi-core processors were commercially available and offered known performance benefits. The claimed flow of information—a second node receiving a call, executing it, and communicating a result to a third node, which in turn could use that result for a subsequent evaluation and return a final result to the first node—was taught by Schreiner1's description of task dependencies, managed by commands like dist[wait].
    • Motivation to Combine: A POSITA would combine the Distributed Maple publications because they describe a single, cohesive project, share a common author, and cross-reference one another. A POSITA would naturally consult the Maple Guide to understand the underlying Maple software that the Distributed Maple system extended. The motivation to incorporate the teachings of the SPARC IV and AMD articles stemmed from the known benefits of using prevalent multi-core hardware to improve the performance of parallel computing systems, a standard design choice for a POSITA at the time.
    • Expectation of Success: Because the Distributed Maple publications described an existing, functional system, a POSITA would have a high expectation of success. Implementing this known system on multi-core processors was a predictable and well-understood technological evolution, not an inventive step.

Ground 2: Obviousness over Distributed Maple Art in view of MPI Standard - Claims 30, 31, and 34 are obvious over the references of Ground 1 in further view of the MPI Standard.

  • Prior Art Relied Upon: The references of Ground 1 in further view of MPI Standard (“MPI: A Message-Passing Interface Standard,” a 1995 standard).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground specifically addressed limitations in claims 30, 31, and 34 related to "asynchronous calls" and "asynchronous behavior." Petitioner asserted that the base combination of references from Ground 1 already taught an inherently asynchronous system, as the Java-based dist.Scheduler component operated independently of the Maple kernel. The addition of the MPI Standard provides a specific, well-known implementation for this asynchronous communication.
    • Motivation to Combine: A POSITA had an explicit and compelling motivation to combine the teachings. Schreiner1 directly stated that implementing the Distributed Maple scheduler using a message-passing library such as MPI "will always yield a more efficient implementation." Furthermore, the ’768 patent itself references the MPI Standard as a basis for its asynchronous communication protocol. Therefore, a POSITA seeking to optimize the Distributed Maple system would have been directly led to implement its peer-to-peer communication layer using the MPI library.
    • Expectation of Success: A POSITA would have a high expectation of success in making this modification. MPI was the de-facto industry standard for high-performance cluster computing. Using its conventional, non-blocking, asynchronous calls (e.g., mpilsend[], mpiIRecv) to implement the communication patterns already described in Distributed Maple would be a straightforward and predictable engineering task.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under the Fintiv factors would be inappropriate. The petition asserted that the parallel district court proceeding was in an early stage, with no depositions taken and no Markman hearing conducted. It noted that the court's trial date was scheduled for after the deadline for a Final Written Decision in the IPR and was subject to further delay. Critically, Petitioner stipulated that it would not pursue the same invalidity grounds in the district court if the IPR was instituted, minimizing any potential overlap. Petitioner also emphasized that the prior art references relied upon in the petition were never considered by the Examiner during the original prosecution of the ’768 patent.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1, 4-10, 18-22, 24-25, 30-31, and 33-34 of Patent 10,333,768 as unpatentable under 35 U.S.C. §103.