PTAB

IPR2021-00123

Microchip Technology Inc v. Bell Semiconductor LLC

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with Silicon-Germanium and Method of Making
  • Brief Description: The ’132 patent discloses a semiconductor device that integrates both a high-performance region containing Silicon-Germanium (Si-Ge) and a standard performance region of pure Silicon on the same substrate. This structure allows high-speed circuits to coexist with legacy or non-speed-sensitive circuits on a single chip.

3. Grounds for Unpatentability

Ground 1: Claims 1, 5, 12, 13, and 16 are anticipated or obvious over Wallace

  • Prior Art Relied Upon: Wallace (Patent 6,784,507)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Wallace discloses all limitations of independent claims 1 and 5. For device claim 1, Wallace teaches an integrated circuit with a silicon substrate, a Si-Ge layer on the substrate, a distinct silicon region without Si-Ge (for NMOS devices), and a distinct Si-Ge region (for PMOS devices), with circuit devices fabricated on both regions. For method claim 5, Wallace teaches the required steps for fabricating such a device, including providing a silicon substrate, forming a thermal oxide layer, masking it, selectively removing the oxide to expose a portion of the substrate, and depositing a Si-Ge layer on that exposed portion via selective epitaxial growth.
    • Motivation to Combine (for §103 grounds): For claim 16, which requires wet etching to remove the thermal oxide layer, Petitioner argued it would be obvious to use this method. Wallace discloses various etching techniques, including “wet etch,” and explicitly teaches using a buffered HF solution—a known wet etchant—to remove residual pad oxide. A POSITA would combine this specific teaching with the general process to predictably and successfully remove the oxide layer.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in using a well-established wet etching technique for its known purpose of selectively removing an oxide layer from a silicon substrate.

Ground 2: Claims 2-4, 6, 17, and 18 are obvious over Wallace in view of Bulsara

  • Prior Art Relied Upon: Wallace (Patent 6,784,507) and Bulsara (Patent 6,891,209)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted Wallace teaches the base device of claim 1, and Bulsara provides the additional elements of dependent claims 2, 3, 6, and 17. Specifically, Bulsara teaches forming a "tensilely strained layer... of silicon" on top of a Si-Ge layer, satisfying the "Silicon layer" limitation of claims 2 and 6. Bulsara also discloses forming a DRAM trench capacitor in a polycrystalline (polysilicon) region and connecting it to the Si-Ge layer, meeting the limitations of claims 3, 4, 17, and 18.
    • Motivation to Combine: A POSITA would combine these references to solve shared problems in enhancing CMOS circuit performance. Wallace explicitly states a goal of achieving "high carrier mobilities." Bulsara teaches that adding a strained silicon layer over the Si-Ge layer is a known technique to further improve carrier mobility. A POSITA would therefore add Bulsara's layer to Wallace's device to achieve Wallace’s stated goal. Additionally, Wallace contemplates memory applications, and Bulsara provides a compatible trench capacitor structure, making the combination logical for creating a device with memory.
    • Expectation of Success: The combination involves applying a known performance-enhancing technique (strained silicon layer) and a standard component (trench capacitor) to a similar device, yielding predictable improvements with a high expectation of success.

Ground 3: Claims 14 and 15 are obvious over Wallace in view of Ernst

  • Prior Art Relied Upon: Wallace (Patent 6,784,507) and Ernst (2002 Symposium on VLSI Technology Digest of Technical Papers)

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Wallace teaches the base method of claim 12 (epitaxially growing a Si-Ge layer). Ernst teaches the additional limitations of claims 14 and 15: doping the Si-Ge layer with carbon within a specific atomic percentage range. Ernst discloses "epitaxially grown Si:C and SiGe:C channel NMOS devices" and discloses a carbon concentration range of 0.9 to 1.6 atomic percent, which overlaps with the claimed range of 0.2 to 1.5 atm %.
    • Motivation to Combine: A POSITA would be motivated to incorporate Ernst's carbon doping into Wallace's fabrication process. Both references concern CMOS devices with Si-Ge channels. Ernst teaches that carbon doping solves the well-known problem of boron diffusion in CMOS fabrication, which improves device performance and reliability. A POSITA would apply this known solution from Ernst to improve the device disclosed in Wallace.
    • Expectation of Success: Applying the known technique of carbon doping to suppress boron diffusion in a CMOS process was a predictable method for improving device performance, giving a POSITA a reasonable expectation of success.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including grounds based on Gonzalez (Patent 6,861,326) alone and various combinations of Wallace, Gonzalez, Lustig (Patent 5,998,807), Gardner (Patent 6,274,442), Bulsara, Ernst, and Coolbaugh (Patent 6,800,921).

4. Key Claim Construction Positions

  • "forming a Si-Ge layer" (Claim 5): Petitioner noted that in parallel district court litigation, the Patent Owner interpreted method step 5[e] ("removing at least a portion of the thermal oxide layer") and 5[f] ("forming a Si-Ge layer on the exposed portion") as a subset of step 5[b] ("depositing Si-Ge on the Silicon substrate"). For the purposes of the IPR petition only, Petitioner adopted this broad interpretation, which requires only a single step of forming Si-Ge, while reserving the right to argue for a different construction in court.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, asserting that multiple factors weigh in favor of institution. The parallel district court case was in its infancy at the time of filing, with minimal investment from the parties. A Final Written Decision from the IPR would likely issue before the conclusion of the district court trial. Petitioner also stipulated that it would not pursue in district court any invalidity grounds raised or that could have been reasonably raised in the IPR, thereby avoiding overlap. Finally, Petitioner contended the grounds are strong and IPR is a more efficient forum for resolving the complex semiconductor technology issues for two separate district court cases.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-18 of the ’132 patent as unpatentable.