Google LLC v. Singular Computing LLC

1. Case Identification

• Case #: IPR2021-00154
• Patent #: 10,416,961
• Filed: October 30, 2020
• Petitioner(s): Google LLC
• Patent Owner(s): Singular Computing LLC
• Challenged Claims: 1-5, 10-16, 21-27

2. Patent Overview

• Title: Low Precision High-Dynamic Range Processing
• Brief Description: The ’961 patent discloses a device comprising at least one "low precision high-dynamic range" (LPHDR) execution unit. The execution unit is functionally defined by its ability to perform a mathematical operation (e.g., multiplication) with a specified minimum level of imprecision (at least 0.2% error) over a high dynamic range of input values.

3. Grounds for Unpatentability

Ground 1: Claims 1-5, 10-16, and 21-27 are obvious over Bates-2010.

• Prior Art Relied Upon: Bates-2010 (Application # 2010/0325186).
• Core Argument for this Ground: Petitioner's central argument is that the challenged claims are not entitled to their claimed priority date from the ’201 Application (which published as Bates-2010) because the application fails the written description and enablement requirements of 35 U.S.C. §112. This failure means Bates-2010 qualifies as prior art to the ’961 patent. Petitioner then argued that Bates-2010, as prior art, renders the challenged claims obvious. While Bates-2010 does not explicitly describe a complete embodiment meeting all claim limitations, it discloses the key components and separately suggests the claimed functional performance characteristics, making the final combination obvious to a Person of Ordinary Skill in the Art (POSA).
  • Prior Art Mapping: Bates-2010 discloses a silicon-implemented execution unit that operates on digital representations of numbers using floating-point arithmetic. It describes an implementation with a precision of about 0.1% and a dynamic range ("one millionth up to one million") that meets the range recited in the claims. Separately, Bates-2010 suggests that an LPHDR element can be configured to produce a relative error of at least 0.2% for at least 10% of possible inputs, which maps directly to the functional limitations of independent claim 1. Bates-2010 also discloses a SIMD processor architecture with a control unit, mapping to the "device" and "computing device" limitations.
  • Motivation to Combine (and Modify): A POSA reading Bates-2010 would be motivated to modify the disclosed silicon-based, floating-point execution unit to achieve the explicitly stated and desirable performance characteristics (i.e., the ≥0.2% error for ≥10% of inputs) found in the same document. The motivation was to create a functioning LPHDR unit with the specific error profile that Bates-2010 itself identified as a goal.
  • Expectation of Success: A POSA would have a reasonable expectation of success in making this modification. The art understood that floating-point precision is a function of the number of mantissa bits used. A POSA could have readily used software emulation to determine how to reduce the number of mantissa bits in the disclosed floating-point unit to achieve the target error rates suggested by Bates-2010. This was a predictable design choice, not undue experimentation.

4. Key Technical Contentions (Beyond Claim Construction)

• Lack of Written Description and Enablement for Claimed Genus: Petitioner's primary technical argument, which underpins its assertion that Bates-2010 is prior art, is that the ’961 patent's specification (shared with the ’201 Application/Bates-2010) fails to support the full scope of the claimed genus of "execution units." The claims are defined functionally and are exceptionally broad, covering implementations using conventional silicon transistors as well as nascent, unpredictable technologies (e.g., DNA computing, nanomechanical, optical) and analog computing.
• Failure to Describe Representative Species: Petitioner argued that the specification only describes a single species—a digital, silicon-transistor-based implementation—in any detail, and even that description fails to link specific structures to the claimed functional error rates. It provides no enabling disclosure for the vast majority of the claimed genus, particularly for the non-silicon, analog, or non-deterministic embodiments. The specification's mere "laundry list" of aspirational technologies, without any guidance on how to implement them to achieve the claimed functional result, was argued to be a failure to demonstrate possession of the full invention under §112.

5. Arguments Regarding Discretionary Denial

• Arguments against §314(a) Fintiv Denial: Petitioner contended that discretionary denial under the Fintiv factors would be inappropriate. It argued that the IPR petition was filed expeditiously, just two months after receiving infringement contentions and before preliminary invalidity contentions were due in the parallel district court litigation. Key factors weighing against denial included: no trial date had been set in the district court, which was "very far away from trial"; litigation investment was minimal as fact discovery was in its infancy; and the petition challenged 17 claims not asserted in the litigation, meaning the IPR would resolve issues beyond the scope of the court case.
• Arguments against §325(d) Denial: Petitioner argued denial under §325(d) was improper because the petition presented art and arguments not previously considered by the USPTO. The core of the petition was a priority-based challenge, arguing the examiner materially erred by affording the ’961 patent a priority date to which it was not entitled under §112. This specific invalidity theory was not before the examiner during prosecution.

6. Relief Requested

• Petitioner requested the Board institute an inter partes review and cancel claims 1-5, 10-16, and 21-27 of the ’961 patent as unpatentable.