Google LLC v. Singular Computing LLC

1. Case Identification

• Case #: IPR2021-00155
• Patent #: 10,416,961
• Filed: October 30, 2020
• Petitioner(s): Google LLC
• Patent Owner(s): Singular Computing LLC
• Challenged Claims: 1-5, 10, 13-14, 21, and 23-25

2. Patent Overview

• Title: Approximate Arithmetic Processing
• Brief Description: The ’961 patent relates to a device comprising at least one "low precision high-dynamic range" (LPHDR) execution unit. The technology focuses on performing arithmetic operations, such as multiplication, with intentional imprecision to reduce power consumption while still supporting a wide dynamic range of numerical values.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 4-5, 10, and 13-14 are obvious over Dockser.

• Prior Art Relied Upon: Dockser (Application # 2007/0203967).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Dockser disclosed all limitations of the challenged claims. Dockser taught a "floating-point processor" (FPP) that performs mathematical operations at a selectable, reduced precision to conserve power, particularly for battery-operated devices. This reduction in precision was achieved by dropping power to the least-significant mantissa bits of the operands, which Petitioner contended was functionally equivalent to the claimed LPHDR execution unit. Petitioner asserted that the standard IEEE-754 floating-point format used by Dockser’s FPP inherently met the claimed dynamic range, and the imprecision resulting from its bit-dropping technique met the claimed relative error limitations.
  • Motivation to Combine (for §103 grounds): This ground was based on a single reference.
  • Expectation of Success (for §103 grounds): This ground was based on a single reference.

Ground 2: Claims 1-2, 4-5, 10, 13-14, 21, and 24-25 are obvious over Dockser in view of Tong.

• Prior Art Relied Upon: Dockser (Application # 2007/0203967) and Tong (a 2000 IEEE journal article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the teachings of Dockser by adding Tong. Tong addressed the same problem of reducing power consumption by optimizing floating-point arithmetic precision. It taught that for many applications, such as speech and image recognition, precision could be significantly reduced—retaining as few as 5 mantissa bits—without substantially impacting overall accuracy. Tong also explicitly taught emulating reduced-precision floating-point units in software to determine the minimal number of bits required, which Petitioner mapped to the limitations of claims 21, 24, and 25.
  • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine Tong’s teachings with Dockser’s device to achieve even greater power savings. A POSITA would have been motivated to configure Dockser’s selectable-precision FPP to operate with the lower mantissa bit-widths that Tong demonstrated were effective and power-efficient for specific, known applications.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because both references provided solutions for the same well-known trade-off between precision and power consumption in floating-point units.

Ground 3: Claims 1-5, 10, and 13-14 are obvious over Dockser in view of MacMillan.

• Prior Art Relied Upon: Dockser (Application # 2007/0203967) and MacMillan (Patent 5,689,677).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground added MacMillan to address claims requiring multiple processing units. MacMillan disclosed a computer system architecture using a Single Instruction Multiple Data (SIMD) subsystem with numerous parallel processing elements, each containing a "floating point accelerator," to achieve supercomputer-level performance in personal computers. Petitioner argued this architecture directly taught a device with multiple execution units operating in parallel, as required by claims 3 and 10.
  • Motivation to Combine (for §103 grounds): A POSITA would have been motivated to implement the "floating point accelerators" in MacMillan’s parallel architecture using Dockser’s power-efficient FPPs. This combination would predictably achieve the high performance of MacMillan's parallel processing while also gaining the power-saving benefits of Dockser's reduced-precision arithmetic, a critical consideration for the types of personal and portable computers targeted by both references.
  • Expectation of Success (for §103 grounds): Success was expected because the combination involved incorporating a known type of specialized processor (Dockser's FPP) into a known parallel computing architecture (MacMillan's) to achieve the recognized and distinct benefits of each technology.

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) over the combination of Dockser, Tong, and MacMillan, arguing it would have been obvious to implement MacMillan's parallel architecture using Dockser's FPPs that were further configured to operate at the highly reduced precision levels taught by Tong.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §314(a) and the Fintiv factors. The core arguments were that the petition was filed expeditiously after the denial of a motion to dismiss in a parallel district court case, that the parallel litigation was in its infancy with no trial date set, and that investment in discovery related to validity was minimal. Petitioner also contended that the strong merits of the petition weighed in favor of institution.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-5, 10, 13-14, 21, and 23-25 of the ’961 patent as unpatentable.