Nanya Technology Corp v. Monterey Research LLC

1. Case Identification

• Case #: Unassigned
• Patent #: 7,158,429
• Filed: November 4, 2020
• Petitioner(s): Nanya Technology Corporation; Nanya Technology Corporation, U.S.A.; Nanya Technology Corporation Delaware
• Patent Owner(s): Monterey Research, LLC
• Challenged Claims: 1-3

2. Patent Overview

• Title: System for Read Path Acceleration
• Brief Description: The ’429 patent discloses a system to accelerate the read path in memory core integrated circuits. The invention claims a specific architecture comprising local amplifiers, global read data lines, a main amplifier, and first and second main amplifier strobes to reduce signal delay during memory read operations.

3. Grounds for Unpatentability

Ground 1: Claims 1-3 are obvious over Winograd in view of Issa or Merritt

• Prior Art Relied Upon: Winograd (Patent 6,646,954), Issa (Patent 6,480,424), and Merritt (Patent 5,598,376).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Winograd discloses a hierarchical, self-timed memory architecture that meets nearly all limitations of claim 1. This includes a memory core divided into segments with local sense amplifiers (LSAs) coupled to global read data lines (gbit/gbit_n lines), a main amplifier (global sense amplifier, or GSA) coupled to those lines, and a main amplifier strobe (genL) coupled to the LSAs. Petitioner further argued that Winograd discloses the limitations of dependent claims 2 and 3, namely a second main amplifier strobe (gbitR) coupled to the main amplifier and an equalization circuit integrated within its sense amplifiers and multiplexer. The only element Petitioner contended Winograd lacks is an explicit disclosure of the main amplifier’s output being coupled to an "output register," instead disclosing an input/output buffer. Both Merritt and Issa were cited as teaching this missing element, disclosing main amplifiers with outputs coupled to output latches or registers.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the output register taught by Merritt or Issa with the Winograd system. The motivation was to simplify the timing and synchronization of read data and to provide a known method for temporarily storing data bits read from memory, which is the conventional function of an output register in such circuits.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in this combination, as incorporating an output register is a standard and predictable design choice in memory architectures that would yield no unexpected results.

Ground 2: Claims 1-3 are anticipated by Merritt

• Prior Art Relied Upon: Merritt (’376 patent).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Merritt, which is directed to high-speed memory architectures, discloses every element of claims 1-3. Petitioner mapped claim 1 by identifying Merritt’s memory core divided into array regions (segments) with associated data sense amplifiers (local amplifiers) coupled to global read lines (LIO/LIO*). These lines feed into a main amplifier (GSA 67) whose output is coupled to an output circuit (output register). For claim 1(c), Petitioner identified Merritt’s write enable signal (WE) as the "main amplifier strobe" that is routed to each local sense amplifier. For claim 2, Petitioner identified the equilibrate signal (EQUIL*) as the "second main amplifier strobe" coupled to the main amplifier. For claim 3, this same EQUIL* signal was shown to be coupled to an equilibration device, meeting the final limitation.

Ground 3: Claims 1-3 are obvious over Manning in view of Merritt

• Prior Art Relied Upon: Manning (Patent 5,729,503) and Merritt (’376 patent).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Manning discloses a memory architecture with a data-path portion that is topographically identical to that shown in Merritt. Manning was alleged to teach a memory core with local and main amplifiers, global read lines, and an output register, thus satisfying most limitations of claim 1. Petitioner argued that Merritt could be used to supply any elements arguably missing from Manning, specifically the "main amplifier strobe coupled to each of the plurality of local amplifiers" (Manning’s write enable signal is not explicitly shown routed to all local amplifiers). Petitioner asserted Merritt clearly discloses its write enable signal (the main amplifier strobe) is routed to each local data sense amplifier.
  • Motivation to Combine: A POSITA would be motivated to modify Manning's device using Merritt’s strobe routing because the two references disclose identical data-path layouts. This shared architecture would make it a simple and logical step to apply Merritt's more explicit strobe control scheme to Manning's system to ensure reliable, high-speed operation, which is the goal of both patents.
  • Expectation of Success: Because the core data-path layouts were asserted to be identical, a POSITA would expect the combination to work predictably to accelerate the read path without unexpected results. The same logic was applied to the dependent claims, using Merritt to supply the second strobe and its coupling to an equalization circuit.

• Additional Grounds: Petitioner asserted numerous additional grounds of unpatentability. These included anticipation of claim 1 by Issa and multiple obviousness challenges against claims 1-3 based on different combinations of the primary references, as well as additional art including Monzel (Patent 6,667,912), McClure (Patent 5,802,004), and Kawasumi (Patent 6,424,554). These grounds relied on similar rationales of combining known memory circuit elements to achieve predictable improvements in speed and performance.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3 of Patent 7,158,429 as unpatentable under 35 U.S.C. §102 and §103.