PTAB

IPR2021-00344

Micron Technology Inc v. Unification Technologies LLC

Key Events

Petition

petition Intelligence

Title: Systems and Methods for Persistent Deallocation
Brief Description: The ’658 patent discloses systems for managing data in non-volatile storage, such as flash memory. The invention involves receiving a message (e.g., a TRIM command) indicating that data associated with a logical identifier has been erased from a user's perspective, and in response, storing a persistent indication of this erasure without necessarily physically deleting the data immediately, thereby improving efficiency.

Prior Art Relied Upon: Bennett (Patent 7,624,239).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Bennett taught all limitations of the challenged claims. Bennett disclosed a memory controller that, upon receiving an erase command specifying logical sectors (the claimed "logical identifier"), could perform a "logical erase" instead of an immediate, time-consuming physical erase. This logical erase involved setting a flag or otherwise marking the data as erased in a Group Address Table (GAT) stored in non-volatile flash memory. Petitioner asserted this directly mapped to the claimed invention of receiving a message and storing a persistent indication that the associated data is erased.
- Motivation to Combine (for §103 grounds): As a single-reference ground, the argument relied on the general knowledge of a person of ordinary skill in the art (POSITA) to understand that Bennett's disclosed system met the claim limitations. For example, a POSITA would have understood that an erase command from a host computer implies that, from the user's perspective, the data has been deleted.
- Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as Bennett explicitly described the claimed functionality for managing erase operations in non-volatile memory.

Prior Art Relied Upon: Suda (Patent 7,057,942).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Suda, like Bennett, disclosed the core claimed concepts. Suda taught a memory device that, to avoid lengthy physical erasures, responded to an erase command by writing "erasure area pointers" to designate a range of logical addresses as being in a "virtual erased" state. These pointers, indicating the data is to be treated as erased, were stored persistently in non-volatile flash memory to survive power-off events. Petitioner argued this system of receiving a command and persistently storing pointers that indicate a "virtual erased" state met all limitations of independent claim 1.
- Motivation to Combine (for §103 grounds): This ground was also based on a single primary reference. Petitioner argued a POSITA would have understood that Suda’s teachings on managing data erasure with persistent pointers rendered the challenged claims obvious. For dependent claims related to index reconstruction, a POSITA would have known to apply the same power-off preservation technique Suda taught for erasure pointers to its logical-to-physical address tables.
- Expectation of Success (for §103 grounds): A POSITA would have expected success in implementing the claimed system, as Suda described a complete, functional memory management device.

Prior Art Relied Upon: Suda (Patent 7,057,942) and SwSTE’05 (an IEEE conference publication by Gal et al.).
Core Argument for this Ground:
- Prior Art Mapping: This ground specifically addressed limitations in dependent claims related to an "index reconstruction module." While Suda disclosed the core functionality, Petitioner argued that SwSTE’05, a survey of flash memory technology, explicitly taught the reconstruction techniques claimed. SwSTE’05 described the standard practice of storing an "inverse map" on the flash device itself to reconstruct the main logical-to-physical mapping table ("direct map") in RAM upon device initialization. This combination provided an explicit basis for the claimed reconstruction features.
- Motivation to Combine (for §103 grounds): A POSITA would combine Suda and SwSTE’05 because both addressed improving flash memory performance. It would have been obvious to apply the standard reconstruction technique from SwSTE’05 to Suda’s system to ensure its logical-to-physical address table was preserved across power cycles—the very same reason Suda already provided for persistently storing its erasure area pointers.
- Expectation of Success (for §103 grounds): The combination would have yielded predictable results, as it involved applying a well-known, standard technique (from SwSTE’05) to a compatible system (Suda) to solve a known problem (data persistence).

For the purposes of the petition, Petitioner adopted the Patent Owner's proposed constructions for certain terms to demonstrate invalidity even under the Patent Owner's interpretation.
"data associated with the logical identifier [has been/is] erased": Petitioner adopted the Patent Owner's apparent position that this term refers to data that appears deleted from a user's perspective (e.g., a file deleted from a document), even though the data physically remains on the storage device.
Indefiniteness: Petitioner argued several terms, including "storage module" and "marking module," were indefinite under 35 U.S.C. §112(f) for lacking corresponding structure, but proceeded with the invalidity analysis using the Patent Owner's proposed constructions, which interpreted them as functional hardware/software modules within a storage controller.

Petitioner argued that discretionary denial under Fintiv was unwarranted due to several factors.
Overlap: Petitioner stipulated that if the IPR were instituted, it would not pursue the same invalidity grounds or prior art references in the parallel district court litigation, strongly mitigating any concerns of inefficiency.
Stage of Litigation: The parallel district court case was in a very early stage, with no substantive rulings, no claim construction order, and discovery not yet open.
Merits: Petitioner asserted the petition presented strong evidence of unpatentability, weighing in favor of institution to protect the integrity of the patent system.

Petitioner requested the institution of an inter partes review and the cancellation of claims 1-5, 8-12, and 22-26 of Patent 8,762,658 as unpatentable under 35 U.S.C. §103.