PTAB

IPR2021-00345

Micron Technology Inc v. Unification Technologies LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Systems and Methods for Identifying Storage Resources That Are Not In Use
  • Brief Description: The ’727 patent discloses a non-volatile solid-state storage system, such as a flash memory drive, that includes a controller and an "indexer." The indexer manages logical-to-physical address mapping and is configured to remove an address assignment in response to a message from a host system indicating that a logical address has been erased.

3. Grounds for Unpatentability

Ground 1: Claims 1-6 and 12-16 are obvious over Bennett in view of POSITA knowledge.

  • Prior Art Relied Upon: Bennett (Patent 7,624,239).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bennett teaches every element of the challenged claims. Bennett discloses a flash memory system with a controller that manages a "Group Address Table" (GAT) to map logical sectors to physical "metablocks." Petitioner asserted this GAT and its managing controller functions as the claimed "indexer." Bennett describes receiving an "erase command" from a host, which corresponds to the claimed "message." In response, Bennett's system handles the command by either physically erasing a full block or "logically erasing" a partial block by setting an "erased" flag in the GAT. Petitioner contended this flag-setting mechanism meets the limitation of "remov[ing] an assignment" between the logical and physical address.
    • Motivation to Combine (for §103 grounds): This ground primarily relied on Bennett, with POSITA knowledge supplying well-known industry standards. For example, for claim 6's "bus interface," Petitioner argued a POSITA would find it obvious to use a standard interface like SATA, which was ubiquitous at the time, to couple Bennett's controller to a host for high-speed communication and broad compatibility.
    • Expectation of Success: A POSITA would have a high expectation of success in implementing Bennett's memory management system with standard components like SATA interfaces, as these were well-established and designed for such integration.

Ground 2: Claims 1-3, 5-6, and 12-16 are obvious over Suda in view of POSITA knowledge.

  • Prior Art Relied Upon: Suda (Patent 7,057,942).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Suda discloses a memory device with a flash memory controlling section that manages a "logical and physical address table," which functions as the claimed "indexer." Suda's controller receives an "erase command" from a host device. In response, instead of performing a slow physical erasure, the controller uses "erasure area pointers" to mark the relevant data range as being in a "virtual erased" state, deferring the actual erasure. Petitioner asserted this process meets the claim limitations, as the pointers designate data for removal. When a physical block is eventually erased, Suda teaches "canceling the relation" in the address table, directly meeting the "remove an assignment" limitation.
    • Motivation to Combine (for §103 grounds): Similar to Ground 1, this ground relied on Suda plus POSITA knowledge to address elements like the bus interface, arguing it would be obvious to apply known standards to Suda's disclosed system.
    • Expectation of Success: The application of common knowledge, such as using an operating system on a host device (e.g., a digital camera) to issue erase commands, to Suda's system would have been straightforward with a high expectation of success.

Ground 3: Claims 4 and 13 are obvious over Suda in view of Bennett and POSITA knowledge.

  • Prior Art Relied Upon: Suda (Patent 7,057,942) and Bennett (Patent 7,624,239).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claims 4 and 13. For claim 4, which adds that the indexer comprises "firmware," Petitioner argued that while Suda does not explicitly mention firmware, Bennett teaches that a controller's functions are implemented by firmware stored in ROM. A POSITA would combine this by implementing Suda's controller functions using the conventional firmware-based architecture shown in Bennett. For claim 13, which requires storing the "logical-to-physical translation layer" in the flash memory device, Petitioner argued Suda already teaches storing erasure pointers in flash for persistence. Bennett teaches storing the entire address table (GAT) in flash.
    • Motivation to Combine: A POSITA would combine Suda and Bennett to ensure data persistence. It would be obvious to apply Bennett’s more robust technique of storing the entire logical-to-physical address table in non-volatile flash memory to Suda’s system, thereby preventing the loss of mapping information upon power-off, a well-known problem with a conventional solution.
    • Expectation of Success: Combining these known techniques—using firmware for controller logic and storing critical mapping tables in non-volatile memory—were standard design choices in the field, ensuring a high expectation of success.

4. Key Claim Construction Positions

  • Petitioner argued that several key terms, including "indexer," were indefinite but proceeded for purposes of the petition by adopting the Patent Owner's proposed constructions from related district court litigation.
  • "indexer": Petitioner proceeded with Patent Owner's apparent interpretation of "circuitry, software, and/or firmware configured to assign" logical addresses to physical addresses and containing "a map or index."
  • "the identified logical address is erased": Petitioner addressed both its own proposed "plain and ordinary meaning" (that the address itself is erased) and the Patent Owner's construction ("the data identified by the logical address does not need to be preserved"), arguing the prior art met the claim limitations under either interpretation.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. The parallel district court litigation was in a very early stage, with no substantive opinions issued and discovery not yet open.
  • Petitioner submitted a stipulation agreeing not to pursue in district court any invalidity ground raised or that could have been reasonably raised in the IPR if review is instituted. Petitioner argued this stipulation mitigates any concerns about inefficiency or inconsistent rulings, weighing strongly in favor of institution.
  • The merits of the petition are strong, and the complexity of the parallel litigation (involving multiple patents and products) favors the streamlined IPR process to resolve the validity of the challenged claims.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-6 and 12-16 of the ’727 patent as unpatentable.