Samsung Electronics Co Ltd v. Acqis LLC

1. Case Identification

• Case #: IPR2021-00607
• Patent #: RE45,140
• Filed: March 8, 2021
• Petitioner(s): Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
• Patent Owner(s): Acqis LLC
• Challenged Claims: 14-38

2. Patent Overview

• Title: Interconnection Between Computer Systems
• Brief Description: The ’140 patent relates to an interconnection bus, referred to as an XPBus, for connecting separate computer systems or modules. The system transmits control bits rather than dedicated control signals to reduce the number of required signal channels, which in turn allows for the use of low voltage differential signaling (LVDS) for the interface.

3. Grounds for Unpatentability

Ground 1: Obviousness over Chu Combination - Claims 14-38 are obvious over Chu’886 in view of Chu’330.

• Prior Art Relied Upon: Chu’886 (U.S. Provisional Application # 60/083,886) and Chu’330 (Patent 6,345,330).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chu’886 discloses the core architecture of the claimed invention, including a removable "Attached Computer Module" (ACM) with an integrated CPU and graphics controller on a single chip. This ACM connects to a peripheral console via an "Exchange Interface System Bus" (XIS Bus) that includes a video bus and an XPBus. Chu’330, which expressly relates to Chu’886, was asserted to provide the missing details of the bus implementation, teaching that the XIS bus consists of unidirectional LVDS lines that transmit data, including encoded PCI and USB transactions, in a serial bit stream. Petitioner contended that the combination of Chu’886's architecture with Chu’330's LVDS bus implementation renders the challenged claims obvious.
  • Motivation to Combine: A POSITA would combine these references because Chu’330 explicitly identifies Chu’886 as a related application and both were filed by the same inventor. The references address the analogous art of low-pin count, cable-friendly interconnection buses. The motivation would be to implement the bus system of Chu’886 using the superior LVDS technology detailed in Chu’330 to achieve a faster, lower-noise, and more power-efficient interconnection, which directly aligns with the stated goals of the art.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because Chu’886 already provides the foundational bus architecture (XIS Bus and XPBus). Applying the specific LVDS implementation from Chu’330 to this existing architecture would be a predictable improvement.

Ground 2: Obviousness over Huang and Chu’330 - Claims 14, 15, 17-23, 25-31, and 34-38 are obvious over Huang in view of Chu’330.

• Prior Art Relied Upon: Huang (Patent 8,253,750) and Chu’330 (Patent 6,345,330).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Huang discloses a highly integrated digital media processor (DMP) formed on a single chip, which includes a CPU, a GPU (graphics controller), memory interfaces, and various peripheral interfaces like PCI express (PCIe) and USB. Huang further teaches using an LVDS channel to output video data (e.g., TMDS signals) from the chip. Petitioner argued that Huang alone teaches the core limitation of an integrated CPU/graphics controller on a single chip connected to a differential signal channel. Chu’330 was used to supply the teaching of implementing other data buses (like PCIe or USB) with LVDS lines, as Huang’s disclosure of LVDS was limited to video output.
  • Motivation to Combine: A POSITA would combine these analogous art references to improve the performance of Huang’s integrated DMP. The motivation would be to apply the efficient, cable-friendly LVDS bus technology from Chu’330 to the various data interfaces in Huang's DMP, not just the video output. This modification would improve speed, reduce power consumption, and lower electromagnetic interference, representing a known solution to a common problem in integrated circuit design.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in this combination because Huang already successfully implements LVDS for video signals. Extending this known LVDS technology, as detailed by Chu’330, to other data interfaces on the same chip would be a straightforward and predictable enhancement.

4. Key Technical Contentions (Beyond Claim Construction)

• Improper Priority Claim: A central contention of the petition was that the ’140 patent is not entitled to its claimed priority date. Petitioner argued that essential subject matter—specifically the integrated CPU with a graphics controller on a single chip—was improperly incorporated into the patent's lineage via a prohibited "nested" reference from the Chu’886 provisional application.
• Effective Priority Date: Petitioner asserted that because of this improper incorporation, the earliest priority date for the challenged claims is November 10, 2011, the date the subject matter was first explicitly added to an application in the priority chain. This later priority date is critical because it makes Chu’886 and Chu’330, which share an inventor with the ’140 patent, available as prior art under 35 U.S.C. §102(b).

5. Arguments Regarding Discretionary Denial

• Arguments against §325(d) Denial: Petitioner argued the Office erred during prosecution by overlooking the improper incorporation by reference, which led to an incorrect priority date assessment. This error meant the Examiner never properly considered Chu’886 and Chu’330 as prior art. Further, Huang was never presented to the Office.
• Arguments against §314(a) Denial (Fintiv): Petitioner argued that the Fintiv factors strongly favor institution. The co-pending district court litigation was in its early stages, with a distant and uncertain trial date, minimizing concerns of duplicative effort or wasted resources. Petitioner also filed a stipulation agreeing not to pursue in the litigation any invalidity ground raised or that could have been reasonably raised in the IPR. Finally, Petitioner asserted that the merits of the petition are particularly strong due to the priority date issue, weighing heavily in favor of institution to correct a clear patentability error and serve the public interest.

6. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 14-38 of the ’140 patent as unpatentable.