Cisco Systems Inc v. 802 Systems Inc

1. Case Identification

• Case #: IPR2021-00619
• Patent #: 7,013,482
• Filed: March 18, 2021
• Petitioner(s): Cisco Systems, Inc.
• Patent Owner(s): 802 Systems Inc.
• Challenged Claims: 1-4, 11-16, 31-41, 61, and 64-65

2. Patent Overview

• Title: Firewall System for Filtering Data Packets
• Brief Description: The ’482 patent discloses a firewall system for data protection that filters data packets in real time as they are being transmitted, without requiring packet buffering. The system selectively alters packets deemed invalid by corrupting them before transmission is complete.

3. Grounds for Unpatentability

Ground 1: Claims 1-4 are obvious over Carter in view of Maria.

• Prior Art Relied Upon: Carter (Patent 5,386,470) and Maria (Patent 6,092,110).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Carter taught a multiport packet repeater that filters data frames based on access rules while simultaneously receiving and re-transmitting them. If a frame is unauthorized, Carter’s repeater modifies (corrupts) the remainder of the frame on the fly. Maria taught a dedicated packet filter processor used in a common network topology between an external network (e.g., the Internet) and an internal network. Crucially, Maria disclosed a "restrictive mode" that functions as a default-deny rule, dropping any packet that does not affirmatively match an allowed rule. The combination of Carter’s real-time filtering repeater with Maria’s network environment met the preamble limitations. The key limitation of claim 1—altering a packet if a validity determination has not been made by the time the end portion is received—was allegedly rendered obvious by applying Maria’s security-focused default-deny logic to Carter’s system, which must make a filtering decision under strict time constraints.
  • Motivation to Combine: A POSITA would combine Carter's low-latency filtering device with Maria’s common network architecture to provide security at the network boundary. Furthermore, a POSITA would have been motivated to incorporate Maria's default-deny rule into Carter's repeater to resolve the known problem of how to handle a packet when a complex filtering decision cannot be completed before retransmission must begin, thereby improving security.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because applying a known security policy (default-deny) to a known packet filter to handle timing uncertainties was a predictable solution to a known problem.

Ground 2: Claims 11-16, 31-36, 40-41, 61, and 64-65 are obvious over Carter and Maria in view of Salim.

• Prior Art Relied Upon: Carter (Patent 5,386,470), Maria (Patent 6,092,110), and Salim (Patent 6,628,653).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Salim to the primary combination from Ground 1 to address claims requiring a "programmable logic device" (e.g., claim 11) and stateful filtering. Salim taught a packet processing apparatus that uses programmable logic devices, such as Field Programmable Gate Arrays (FPGAs), to implement flexible and updatable packet filtering functions. Salim also disclosed using its device for stateful inspection, such as IP traffic conditioning based on bandwidth usage over time. Petitioner asserted it was obvious to implement the filtering logic of the Carter/Maria combination using the programmable hardware taught by Salim.
  • Motivation to Combine: A POSITA would be motivated to implement the filter of Carter/Maria using Salim's programmable logic to gain known benefits such as increased flexibility, easier field upgrades, and the ability to handle a wider range of protocols and more complex filtering rules. It was a well-known design choice to use FPGAs for high-speed packet processing. Additionally, a POSITA would implement the stateful filtering capabilities described by Salim to provide stronger, context-aware filtering in Carter's device.
  • Expectation of Success: Success was expected because implementing known filtering logic on programmable hardware was a common and well-understood engineering practice that yielded the predictable benefits of flexibility and improved performance.

Ground 3: Claims 37-39 are obvious over Carter, Maria, and Salim in view of Loschke.

• Prior Art Relied Upon: Carter (Patent 5,386,470), Maria (Patent 6,092,110), Salim (Patent 6,628,653), and Loschke (Patent 5,956,336).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Loschke to address claims requiring a "result aggregator logic" (e.g., claim 37). Loschke taught a high-speed comparator circuit that used Content Addressable Memory (CAM) for efficient database lookups. Loschke also expressly disclosed using logic gates (e.g., an AND gate) to combine or aggregate the results from multiple different comparator checks into a single output signal. Further, Loschke taught generating a "completion signal" (an error flag) when a search was completed with no match found.
  • Motivation to Combine: A POSITA would be motivated to implement the database and comparators of the Carter/Maria/Salim filter using Loschke's high-speed CAM architecture to improve performance, a key concern for a real-time filter. To manage the outputs from the multiple filter types (e.g., stateful and non-stateful), a POSITA would have found it obvious to use a simple logic gate as a result aggregator, as explicitly taught by Loschke.
  • Expectation of Success: Implementing high-speed lookups with CAMs and combining logic signals with gates were fundamental techniques in digital circuit design. A POSITA would expect this combination to predictably result in a more efficient and performant packet filter.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §325(d) was inappropriate because the asserted prior art combinations were not previously considered by the USPTO during prosecution.
• Petitioner further argued that discretionary denial under Fintiv was inappropriate. The parallel district court proceeding was in its early stages, with minimal investment by the parties and a trial date nearly a year away and subject to likely delays. Petitioner contended these factors weighed against denial and stipulated that, if the inter partes review (IPR) was instituted, it would not pursue the same invalidity grounds in the district court, mitigating concerns of duplicative efforts.

5. Relief Requested

• Petitioner requested the institution of an IPR trial and the cancellation of claims 1-4, 11-16, 31-41, 61, and 64-65 of the ’482 patent as unpatentable.