Xilinx Inc v. FG SRC LLC

1. Case Identification

• Case #: IPR2021-00633
• Patent #: 7,149,867
• Filed: March 15, 2021
• Petitioner(s): Xilinx, Inc.
• Patent Owner(s): FG SRC LLC
• Challenged Claims: 1-19

2. Patent Overview

• Title: System and Method of Enhancing Efficiency and Utilization of Memory Bandwidth in Reconfigurable Hardware
• Brief Description: The ’867 patent describes a system for improving memory bandwidth in reconfigurable hardware, such as Field-Programmable Gate Arrays (FPGAs). The invention employs a configurable "data prefetch unit" to retrieve only the specific data required for a computation from a larger, slower memory and place it into a smaller, faster memory, thereby reducing unnecessary data traffic.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zhang and Gupta - Claims 1-2, 4-8, and 13-19 are obvious over Zhang in view of Gupta.

• Prior Art Relied Upon: Zhang (X. Zhang et al., Architectural Adaptation for Application-Specific Locality Optimizations, IEEE 1997) and Gupta (R. Gupta, Architectural Adaptation in AMRM Machines, IEEE 2000).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Zhang taught the core elements of the invention, including a reconfigurable processor architecture that integrates programmable logic to customize a memory hierarchy (e.g., L1/L2 caches) and a data prefetcher. Zhang’s prefetcher was disclosed as being configurable to conform to an algorithm's needs, capable of operating independently to hide memory latency, and using scatter/gather techniques to retrieve only necessary data fields, thus matching the format and location of data. Petitioner asserted that Gupta disclosed a specific prototype implementation of the general architecture taught by Zhang. Gupta’s prototype included a prefetch unit implemented in an FPGA, positioned between L1 and L2 cache, to support application-specific prefetching from lower-level memory, thereby providing a concrete, working example of Zhang's concepts.
  • Motivation to Combine: Petitioner asserted a strong motivation to combine these references. Both papers originated from the same ongoing academic research project (MORPH/AMRM), shared a common author (Dr. Gupta), and expressly cross-referenced each other. Gupta was presented as a prototype of the architecture described in Zhang. A person of ordinary skill in the art (POSITA) would naturally look to Gupta’s implementation details when considering the architectural framework of Zhang to solve the common problem of improving memory bandwidth in reconfigurable hardware.
  • Expectation of Success: A POSITA would have had a high expectation of success, as combining the teachings was merely applying the specific prototype details from Gupta to the foundational architecture of Zhang, which originated from the same research team and project.

Ground 2: Obviousness over Zhang, Gupta, and Chien - Claims 3 and 9-12 are obvious over Zhang and Gupta in view of Chien.

• Prior Art Relied Upon: Zhang, Gupta, and Chien (A. Chien and R. Gupta, MORPH: A System Architecture for Robust High Performance Using Customization, IEEE 1996).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Zhang/Gupta combination by adding Chien to address limitations related to multi-processor systems and external shared memory. Petitioner argued Chien, part of the same MORPH project, taught a reconfigurable architecture supporting multiple processing elements coupled to an external "global shared memory." For claim 3, which requires writing processed data to an "external off-processor memory," Chien provided an explicit example of such a memory configuration. For claims 9-12, which recite a "reconfigurable hardware system" with a "common memory," Chien taught how L2 cache could be configured as a shared, common memory among multiple processors in the system.
  • Motivation to Combine: The motivation was similar to Ground 1, as all three papers stemmed from the same research project. Petitioner argued that because Zhang expressly contemplated a multiprocessor system, a POSITA seeking to implement such a system would have been motivated to incorporate the well-known shared memory architecture described by Chien. Chien’s disclosure of a "global shared memory" was one of a finite number of predictable solutions for implementing the main memory of the Zhang/Gupta combination in a multiprocessor context.
  • Expectation of Success: The combination was presented as the predictable integration of compatible components from the same research initiative, ensuring a high expectation of success.

4. Key Claim Construction Positions

• "reconfigurable processor": Petitioner proposed this term be construed as "a computing device that contains reconfigurable components such as FPGAs and can, through reconfiguration, instantiate an algorithm as hardware." This construction emphasizes the hardware's ability to be fundamentally altered to match an algorithm's needs.
• "data prefetch unit": Petitioner proposed this term be construed as "a functional unit that moves data between members of a memory hierarchy," allowing for movements as simple as a copy or as complex as an "indirect indexed strided copy." This construction is rooted in the patent’s specification and encompasses the scatter/gather functionality central to Petitioner's arguments.

5. Arguments Regarding Discretionary Denial

• Petitioner argued strongly against discretionary denial under §314(a) (Fintiv) and §325(d). The petition was filed as a "mirror-image" of a previously instituted IPR (IPR2020-01449, filed by Intel) and included a concurrent motion for joinder.
• Fintiv Factors: Petitioner argued the factors favored institution. The parallel district court litigation against Xilinx was in its infancy, with a trial date set for March 2023, well after the projected Final Written Decision (FWD) date of March 2022 for the Intel IPR. Petitioner contended that minimal resources had been invested in the district court case and stipulated that if joined, it would not pursue the same invalidity grounds in that litigation, mitigating concerns of duplicative efforts.
• Serial Petitions: Petitioner argued this was not an abusive serial petition. It was Xilinx's first challenge to the ’867 patent, and its request for joinder as an understudy was an efficient mechanism that would not prejudice the Patent Owner or unduly burden the Board. Petitioner distinguished its situation from a previously denied petition filed by Amazon, noting that this petition relies on different prior art and arguments that the Board had already deemed strong enough for institution in the Intel IPR.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-19 of the ’867 patent as unpatentable under 35 U.S.C. §103.