Taiwan Semiconductor Mfg Co Ltd v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2021-00735
• Patent #: 7,126,214
• Filed: April 5, 2021
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Limited.
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 1-6 and 26-31

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’214 patent relates to a reconfigurable processor module created by stacking and interconnecting thinned integrated circuit die elements, such as a microprocessor, memory, and a field-programmable gate array (FPGA). Interconnection is achieved using contacts that traverse the thickness of the die elements.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka - Claims 1-2, 4, 6, 26-27, 29, and 31 are obvious over Zavracky in view of Chiricescu and Akasaka.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Zavracky taught vertically stacked and interconnected integrated circuit (IC) functional elements, including microprocessors, memory, and programmable logic devices (PLDs), connected by via holes. Chiricescu, which explicitly built upon Zavracky’s work, disclosed using a stacked memory with a 3D FPGA to accelerate FPGA reconfiguration time. Akasaka taught 3D ICs with tens of thousands of distributed "via holes" to improve signal processing speed and parallelism. Petitioner asserted that this combination taught the claimed module comprising a stacked FPGA and memory (Zavracky and Chiricescu) coupled by a number of contact points distributed throughout the surfaces of the functional elements (Akasaka).
  • Motivation to Combine: A POSITA would combine Zavracky and Chiricescu because Chiricescu expressly used Zavracky's technology to solve the known problem of high FPGA configuration time, yielding the predictable result of accelerated reconfiguration. A POSITA would then be motivated to incorporate Akasaka's teaching of high-density, distributed interconnects into this stack to achieve the predictable advantages of increased bandwidth and processing speed, particularly for parallel processing applications.
  • Expectation of Success: Petitioner contended that success was expected because the combination involved applying known techniques (high-density vias) to a known structure (stacked ICs) to achieve a predictable improvement (increased performance). The underlying technologies were well-established and compatible.

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Satoh - Claims 3 and 28 are obvious over Zavracky in view of Chiricescu, Akasaka, and Satoh.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground incorporated the base combination of Zavracky, Chiricescu, and Akasaka from Ground 1. It added the teachings of Satoh, which disclosed using an FPGA to generate and supply a "test stimulus" to a memory array on the same chip for testing purposes. Petitioner argued this combination taught the limitation of using the contact points to provide a test stimulus from the FPGA to another functional element, such as a memory array.
  • Motivation to Combine: Petitioner argued that stacking multiple functional elements, as taught by the primary combination, was known to increase the risk of module failure and reduce manufacturing yield. A POSITA would have recognized the need to test the co-stacked memory. Satoh provided a known solution for improving yield by using an on-chip FPGA for testing. A POSITA would combine Satoh's teaching with the primary combination to gain the predictable benefits of rigorous testing, improved yield, and reduced costs without needing a separate test chip.
  • Expectation of Success: Success was expected as using an FPGA to test circuitry was a well-known and routine technique. Applying this known testing method to the 3D stack of the primary combination would have been a straightforward and predictable implementation.

Ground 3: Obviousness over Zavracky, Chiricescu, Akasaka, and Alexander - Claims 5 and 30 are obvious over Zavracky in view of Chiricescu, Akasaka, and Alexander.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Alexander (a 1995 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground also built upon the base combination from Ground 1. It added the teachings of Alexander, which disclosed building a 3D FPGA by stacking multiple 2D FPGA dies and vertically interconnecting them. This addressed the claims requiring a third IC functional element that includes "another field programmable gate array."
  • Motivation to Combine: Petitioner asserted that a POSITA would be motivated to enhance the parallel processing capabilities of the base 3D stack. Alexander taught that using multiple stacked FPGAs was a preferable method for parallel processing applications compared to general-purpose microprocessors. A POSITA would therefore modify the base combination by adding another FPGA layer as taught by Alexander to upgrade the module's performance for such applications.
  • Expectation of Success: Petitioner argued that a POSITA would have had a high expectation of success. The structure in Alexander was analogous to the base combination (stacked elements with vertical interconnects). Adding another FPGA layer would be a predictable modification, similar to the known practice of stacking multiple memory or microprocessor layers.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §325(d), stating that none of the asserted prior art references or combinations were considered by the USPTO during prosecution of the ’214 patent.
• Petitioner further argued that discretionary denial under Fintiv was inappropriate. The co-pending district court litigation was in an early stage, with a trial date scheduled for May 2022, months after the projected March 2022 Final Written Decision (FWD) in the IPR. Petitioner also noted its stipulation to not pursue the same invalidity grounds in the district court if the IPR is instituted, thereby avoiding parallel litigation on overlapping issues.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-6 and 26-31 of the ’214 patent as unpatentable.