Taiwan Semiconductor Mfg Co Ltd v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2021-00738
• Patent #: 6,781,226
• Filed: April 5, 2021
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Limited
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 1-30

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’226 patent discloses a reconfigurable processor module created by stacking thinned integrated circuit die elements, such as a microprocessor, memory, and a field programmable gate array (FPGA). The stacked die elements are interconnected using contact points that traverse the thickness of the dies.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka - Claims 1-6 are obvious over Zavracky in view of Chiricescu and Akasaka.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Zavracky taught the core concept of a three-dimensional processor module with vertically stacked and interconnected integrated circuits, including microprocessors, memory, and programmable logic devices (PLDs), which a POSITA would understand to include FPGAs. Chiricescu, from the same research group as Zavracky’s inventors, explicitly described building 3D layered FPGAs with stacked memory to improve performance. Akasaka taught 3D ICs with tens of thousands of distributed "via holes" (contact points) to increase interconnection density and accelerate data processing. The combination of these references, Petitioner asserted, disclosed all limitations of independent claim 1, including a processor module with a stacked FPGA and microprocessor electrically coupled by distributed contact points to achieve accelerated data processing.
  • Motivation to Combine: A POSITA would combine Zavracky and Chiricescu because Chiricescu explicitly built upon Zavracky’s technology to solve the known problem of high FPGA configuration times by using stacked memory. A POSITA would further incorporate Akasaka’s teaching of high-density, area-wide interconnects to improve the bandwidth and parallel processing capabilities of Zavracky’s stacked module, a predictable improvement suggested by Akasaka itself.
  • Expectation of Success: Petitioner contended that a POSITA would have a reasonable expectation of success because the combination involved integrating teachings from the same research group (Zavracky and Chiricescu) and applying a well-established technique (Akasaka's distributed vias) to achieve the predictable benefits of improved speed and density.

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Satoh - Claims 7-12 are obvious over the combination of Ground 1 in view of Satoh.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination in Ground 1 and added Satoh to address the limitations of independent claim 7, which required the FPGA to be configured to provide test stimulus to the microprocessor during manufacture and prior to packaging. Petitioner argued Satoh explicitly taught a method of using an on-chip FPGA to generate test signals and expected values to test a co-located CPU (microprocessor) during manufacturing to improve yield.
  • Motivation to Combine: A POSITA would recognize that multi-die stacks increase the risk of module failure and would be motivated to test the stack during manufacture to avoid the expense of packaging defective units. Petitioner asserted that a POSITA would combine Satoh's method with the Zavracky-Chiricescu-Akasaka stack to gain the known benefits of rigorous testing without the additional expense, chip real estate, and design complexity of a separate testing chip.
  • Expectation of Success: Success was expected because using an FPGA for testing was a known and routine application, and its function was not dependent on whether the chip architecture was 2D or 3D.

Ground 3: Obviousness over Zavracky, Chiricescu, Akasaka, and Trimberger - Claims 13-30 are obvious over the combination of Ground 1 in view of Trimberger.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Trimberger (a 1997 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Trimberger to address the limitations of independent claims 13 and 22, which recited a "means for reconfiguring the programmable array within one clock cycle." Petitioner argued that Trimberger taught a time-multiplexed FPGA with on-chip memory and a wide data configuration port that enabled the entire configuration of the FPGA to be changed in a single memory cycle, updating all logic and interconnect bits simultaneously.
  • Motivation to Combine: A POSITA would be motivated to solve the "high configuration time" bottleneck identified by Chiricescu. Trimberger provided a direct solution by teaching an ultra-fast, single-cycle reconfiguration architecture. Petitioner argued a POSITA would integrate Trimberger’s architecture into the 3D stack of the primary combination to enable real-time applications that require rapid reconfiguration without dropping data.
  • Expectation of Success: Combining a known 3D stack with a known method for fast reconfiguration to achieve the predictable result of a fast-reconfiguring 3D module would have been a straightforward design choice with a high expectation of success.

4. Key Claim Construction Positions

• Petitioner argued that two means-plus-function terms required construction under 35 U.S.C. § 112, ¶ 6 (pre-AIA).
• “means for reconfiguring the programmable array within one clock cycle” (claim 13) and “means for updating the plurality of configuration logic cells within one clock cycle” (claim 22): Petitioner contended these were synonymous and that the ’226 patent disclosed two corresponding structures:
  • 1. A wide configuration data port used to update logic cells through an associated configuration memory and buffer cell.
  • 2. A stacked FPGA die and memory die interconnected by a wide configuration data port using contact points distributed throughout the dies.

5. Arguments Regarding Discretionary Denial

• Petitioner presented arguments that discretionary denial under §325(d) and §314(a) (considering General Plastic and Fintiv factors) would be inappropriate.
• The prior art combinations relied upon in the petition were not considered by the examiner during prosecution, which involved no rejections.
• The trial date in the co-pending district court litigation (May 23, 2022) was set for months after the Board’s projected Final Written Decision (March 2022), favoring institution under Fintiv. Petitioner also submitted a stipulation to avoid parallel litigation on overlapping issues.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-30 of the ’226 patent as unpatentable.