PTAB

IPR2021-00942

Micron Technology Inc v. Unification Technologies LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Systems And Methods For Identifying Storage Resources That Are Not In Use
  • Brief Description: The ’727 patent discloses systems for managing solid-state storage devices (SSDs). The technology involves a host system sending a message or command to an SSD controller to indicate that certain logical addresses are erased or no longer contain valid data, allowing the SSD to optimize storage operations like garbage collection.

3. Grounds for Unpatentability

Ground 1: Claims 1-6 and 12-16 are obvious over the Shu Patent, the Shu Trim Proposals, and Jenett (incorporating Ban).

  • Prior Art Relied Upon: Shu (Patent 9,207,876), Shu Trim Proposals (T13 standard proposals, rev. 0-1, from 2007), and Jenett (Patent 6,014,724), which incorporates Ban (Patent 5,404,485) by reference.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of references taught all limitations of the challenged claims. Shu taught a host system sending a "remove-on-delete" command to an SSD to identify invalid data, improving performance by avoiding unnecessary operations on that data during merge/garbage collection cycles. Jenett, which incorporated the foundational flash translation layer (FTL) teachings of Ban, provided the generic architecture of an SSD, including a controller (indexer) that uses a map (logical-to-physical translation layer) to assign logical addresses to physical addresses. The Shu Trim Proposals, which correspond to the command in Shu, explicitly disclosed the format of the command, including using a logical block address (LBA) to identify the invalid data, and taught that a read request to a trimmed block should return zeros.
    • Motivation to Combine: A POSITA would combine these references because Shu explicitly taught implementing its "new functionality" in existing flash memory devices, such as those described by Jenett and Ban, to improve performance. Identifying invalid data was a known problem, and Shu's command offered a more efficient solution than Jenett's method of sending an entire file indication map. A POSITA would have looked to the Shu Trim Proposals for implementation details, as they were submitted to the relevant ATA standards body (T13) to standardize the command taught in the Shu patent.
    • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying a new command (Shu) to a well-understood SSD architecture (Jenett/Ban) to achieve the predictable benefit of improved efficiency. The fact that the industry adopted this exact approach in the ATA standard as the "TRIM" command confirmed its feasibility.

Ground 2: Claims 1-6 and 12-16 are obvious over the Shu Patent, the Shu Trim Proposals, Ban, and further in view of Jenett.

  • Prior Art Relied Upon: Shu (Patent 9,207,876), Shu Trim Proposals (T13 standard proposals, rev. 0-1, from 2007), Ban (Patent 5,404,485), and Jenett (Patent 6,014,724).
  • Core Argument for this Ground: This ground was presented as an alternative to Ground 1 in the event the Board did not find that Jenett incorporated the relevant sections of Ban by reference. Petitioner argued that a POSITA would have been separately motivated to combine Jenett and Ban with the Shu references for the same reasons articulated in Ground 1. The motivation to combine Jenett and Ban was to improve upon Ban's foundational FTL system with Jenett's more advanced method of identifying invalid data.

4. Key Claim Construction Positions

  • Petitioner stated that claim construction disputes did not affect the outcome of the petition. For the purposes of the IPR, Petitioner adopted the Patent Owner's proposed constructions to demonstrate that the claims were invalid even under the Patent Owner's interpretation.
  • A key term was "the identified logical address is erased" (claim 1). Petitioner adopted the Patent Owner's position that this means "the data identified by the logical address does not need to be preserved."

5. Key Technical Contentions (Beyond Claim Construction)

  • A central contention of the petition was that the ’727 patent was not entitled to its claimed priority date of December 6, 2006. Petitioner argued that the 2006 Provisional application failed to provide adequate written description support under §112 for several key limitations added during prosecution.
  • Specifically, the 2006 Provisional allegedly lacked support for an "indexer" or "logical-to-physical translation layer" being located within the solid-state storage controller, for receiving a command that includes a range of logical block addresses, and for updating the translation layer in response to that command.
  • Petitioner contended the earliest effective priority date was September 22, 2007. This later priority date rendered the Shu patent (based on an April 2007 provisional) and the Shu Trim Proposals (published in April and July 2007) valid prior art against the challenged claims.

6. Arguments Regarding Discretionary Denial

  • Petitioner argued that the grounds were not cumulative to issues examined during prosecution because the Examiner was never presented with the early versions of the Shu Trim Proposals. The applicant only disclosed a later version of the proposal that post-dated the claimed priority date, so the Examiner had no reason to consider it as prior art.
  • Petitioner also distinguished this petition from a parallel IPR (IPR2021-00345) by noting that the prior petition did not challenge the patent's priority date and therefore relied on different prior art. This petition's central focus on the priority date challenge necessitated a new proceeding with different references.

7. Relief Requested

  • Petitioner requested institution of an IPR and cancellation of claims 1-6 and 12-16 of Patent 9,632,727 as unpatentable.