PTAB

IPR2021-01265

Microchip Technology Inc v. HD Silicon Solutions LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Transitioning To And From A Sleep State Of A Processor
  • Brief Description: The ’404 patent discloses reducing a processor’s static power consumption by providing a "sleep voltage" that is lower than an operating voltage when the processor's clock is stopped. The technology involves using pairs of sleep and operating voltages, where a voltage regulator transitions between them based on specified timing relationships.

3. Grounds for Unpatentability

Ground 1: Obviousness over NEC-Databook and Stratakos - Claims 1-21 are obvious over NEC-Databook in view of Stratakos and the knowledge of a Person of Ordinary Skill in the Art (POSITA).

  • Prior Art Relied Upon: NEC-Databook (a 1990 single-chip microcomputer databook) and Stratakos (a 1998 doctoral dissertation on high-efficiency DC-DC conversion).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of the prior art references taught every limitation of the challenged claims.
      • NEC-Databook disclosed the µPD751xx family of microcomputers, which included a processing unit capable of entering a low-power "Data Retention mode." In this sleep state, the processor clock was stopped, and the supply voltage was lowered to a level sufficient to maintain the processor's state but insufficient for active operation (e.g., from an operating range of 2.7-6.0V down to a retention voltage of 2.0V).
      • Stratakos disclosed a dynamically adjustable voltage regulator, a "DVS converter," designed to supply a processor with a range of voltages (1.08V to 3.78V) to manage power consumption. Stratakos showed that the time required to transition between voltages was dependent on the voltage difference and provided timing diagrams illustrating these transitions (e.g., a "low-to-high tracking time of 23.5 µs" for a full-scale voltage transition).
      • To meet the limitations of independent claim 1, Petitioner mapped NEC-Databook’s processor and its sleep mode to the claimed system. It then argued a POSITA would use Stratakos's DVS converter to supply the necessary voltages. Petitioner selected exemplary voltages disclosed or suggested by the references: a 2.0V sleep voltage, a 3.3V "second operating voltage," and a 3.78V "first operating voltage."
      • Based on an exemplary "allowed time" of 15 µs (which Petitioner argued a POSITA would derive from system exit latency requirements for real-time processing), Petitioner used the timing data from Stratakos's figures to demonstrate that the key claimed relationships were met. The transition from the sleep voltage (2.0V) to the second operating voltage (3.3V) took approximately 12.4 µs, which is within the 15 µs allowed time. The transition from the sleep voltage (2.0V) to the first operating voltage (3.78V) took approximately 17.4 µs, which is greater than the 15 µs allowed time.
      • Petitioner asserted that the limitations of the dependent claims and other independent claims (7, 11, 15, and 18) were met by analogous combinations and reasoning, relying on the same core teachings for voltage levels, timing, and system configuration.
    • Motivation to Combine (for §103 grounds): Petitioner argued a POSITA would have been motivated to combine the references to implement a known power-saving technique. NEC-Databook taught a processor designed for variable voltage operation to save power but did not detail a specific voltage regulator. Stratakos taught a dynamic voltage regulator for the express purpose of saving power in processors. Therefore, a POSITA would have found it obvious to use Stratakos's advanced regulator with NEC-Databook’s processor to achieve the predictable result of enhanced power management.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because the combination involved applying a known component (a dynamic voltage regulator) to a known system (a processor with low-power states) to achieve a predictable improvement in power efficiency without requiring substantial modification or invention.

4. Key Technical Contentions (Beyond Claim Construction)

  • Establishing an "Allowed Time": A central contention was defining the claim term "allowed time for transitioning from a sleep state to an operating state." Petitioner argued the ’404 patent provided only a single, unsupported example (50 µs) and no clear definition. Petitioner contended that a POSITA would have understood this term to refer to a maximum system exit latency, a parameter dictated by the system's application (e.g., interrupt response time). Based on this understanding and contemporaneous knowledge of real-time systems, Petitioner established an exemplary "allowed time" of 15 µs, which was critical to demonstrating how the transition times disclosed in Stratakos met the specific timing requirements of the claims.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate for several reasons:
    • The estimated district court trial date (December 5, 2022) was scheduled after the statutory deadline for a Final Written Decision (FWD) and was likely to be delayed further due to court backlogs.
    • The petition was filed diligently, just under seven months after the complaint was served and before significant investment in the district court proceeding, such as claim construction hearings or substantive rulings.
    • The IPR addressed all 21 claims of the ’404 patent, providing a more efficient and complete resolution than the parallel litigation, where only a subset of claims was asserted.
    • The petition presented a strong case for unpatentability on the merits, which weighed in favor of institution.

6. Relief Requested

  • Petitioner requested institution of an inter partes review (IPR) and cancellation of claims 1-21 of the ’404 patent as unpatentable.