PTAB

IPR2021-01301

Advanced Micro Devices Inc v. Future Link Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Testing Interconnects
  • Brief Description: The ’108 patent relates to methods for testing the electrical interconnects between integrated circuits (ICs) on a carrier like a printed circuit board. The disclosed invention uses a dedicated "test unit" within an electronic circuit to test these connections, proposing that a low-complexity memory or combinatorial logic can serve as this test unit to improve efficiency, particularly when testing high-complexity ICs or those lacking built-in boundary-scan test circuitry.

3. Grounds for Unpatentability

Ground 1: Obviousness over Cuppens and Bhavsar - Claims 1-3, 8, and 11-13 are obvious over Cuppens in view of Bhavsar.

  • Prior Art Relied Upon: Cuppens (Patent 4,862,418) and Bhavsar (a 1991 IEEE paper titled "Testing Interconnections to Static RAMs").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Cuppens disclosed an electronic circuit with a main unit (EEPROM) and a separate "test unit" (a low-complexity SRAM) used for post-production reliability testing, which operates in distinct normal and test modes. However, Cuppens did not detail interconnect testing. Bhavsar addressed this gap by teaching a method for testing the interconnects of a non-compliant component (like an SRAM) by using an adjacent, boundary-scan-compliant component (like a processor) to send and receive test data. The combination of Cuppens’s circuit architecture with Bhavsar’s interconnect testing methodology allegedly rendered the claims obvious.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine these references to achieve comprehensive testing. Cuppens focused on testing internal selection circuits, while Bhavsar focused on testing external interconnects. A POSITA would recognize the need to test both for a memory circuit to function reliably. Bhavsar expressly proposed its method for testing SRAMs—the exact type of low-complexity memory Cuppens used as a test unit. This created a direct suggestion to apply Bhavsar’s interconnect test to the circuit in Cuppens.
    • Expectation of Success: A POSITA would have a reasonable expectation of success, as the combination involved applying a known testing technique (Bhavsar) to a known circuit configuration (Cuppens), yielding the predictable result of a circuit with enhanced testing capabilities.

Ground 2: Anticipation by Hong - Claims 1, 3, 6-8, 10, and 11 are anticipated by Hong.

  • Prior Art Relied Upon: Hong (Patent 4,241,307).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Hong disclosed every limitation of the challenged claims. Hong described a "Module Interconnection Testing Scheme" where each module (an "electronic circuit") on a board contained a main unit ("logic circuits") for normal operation and a test unit (an Exclusive-OR (XOR) circuit and a shift register) for testing interconnects. Hong taught switching between a normal mode and a test mode via control signals. In the test mode, the test unit was logically connected to the I/O nodes to receive test patterns and output results. Petitioner argued that Hong’s combinatorial XOR circuit met the ’108 patent’s description of a test unit operable as a "low complexity memory." Hong’s method of applying binary patterns and monitoring the XOR output for faults constituted the claimed method of putting test data on interconnects and operating the test unit. For claim 3, Hong’s disclosure of a shift register for capturing and reading out test results met the "read/write register" limitation.

Ground 3: Obviousness over Hong and Wakerly - Claim 4 is obvious over Hong in view of Wakerly.

  • Prior Art Relied Upon: Hong (Patent 4,241,307) and Wakerly (a 1994 textbook, "Digital Design Principles and Practices").
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground specifically addressed dependent claim 4, which required the test unit’s combinatorial circuit to implement an XNOR function. Petitioner acknowledged that Hong’s primary embodiment disclosed an XOR function. Wakerly, a standard textbook on digital design, taught that XOR and XNOR gates are fundamental, functionally inverse circuits commonly used for parity checking.
    • Motivation to Combine: A POSITA would understand from Hong’s disclosure that its XOR tree was a standard parity-checking circuit. Wakerly taught that both XOR and XNOR gates could be used for parity checking, making them well-known, interchangeable design choices. A POSITA would combine Hong with Wakerly's teachings by substituting the XOR gates with XNOR gates, which was a simple design choice to achieve the same testing function with predictable results.
    • Expectation of Success: The substitution of an XOR circuit with its functional inverse, XNOR, was a basic and predictable modification for a digital circuit designer.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under the Fintiv factors was inappropriate. The district court trial date was merely an "estimate" set far in the future and was unlikely to precede a Final Written Decision (FWD) from the Board. Furthermore, Petitioner stipulated that it would not pursue the same invalidity grounds in the parallel district court litigation, which favored institution. Finally, Petitioner contended the merits of the petition were exceptionally strong and that this was the sole challenge to the ’108 patent before the Board, weighing heavily in favor of institution.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-4, 6-8, and 10-13 of Patent 6,622,108 as unpatentable under 35 U.S.C. §102 and/or §103.