PTAB

IPR2021-01396

Qualcomm Inc v. Future Link Systems LLC

Key Events

Petition

petition

Title: Packet Ordering on a Bus
Brief Description: The ’680 patent discloses a system and method for ordering data packets on a communications bus using a two-step process. The method first applies a protocol-based ordering (e.g., standard PCI or PCI Express rules) via a "protocol arbiter" and subsequently applies a performance-based ordering (e.g., based on timestamps or destination) via a "performance arbiter" to improve system performance.

Prior Art Relied Upon: Guthrie (6,327,636).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Guthrie discloses every limitation of the challenged claims. Guthrie teaches a Pipelined Read Transfer ("PRT") system that first complies with standard Peripheral Component Interconnect ("PCI") ordering rules, which Petitioner mapped to the claimed "protocol-based ordering." Guthrie then adds "new ordering requirements" specifically for PRT transactions to "improve performance" and "insure...system optimization." Petitioner asserted these additional, separate PRT rules correspond directly to the claimed "performance-based communications order." Petitioner noted that Patent Owner had previously admitted in another proceeding that Guthrie discloses "protocol-based ordering as claimed."
- Motivation to Combine (for §103 grounds): Not applicable as this ground relies on a single reference. Petitioner argued that Guthrie's combination of standard PCI rules with additional performance-enhancing PRT rules rendered the claimed invention obvious.
- Expectation of Success (for §103 grounds): Not applicable.

Prior Art Relied Upon: Guthrie (’636) and O'Connor (7,120,714).
Core Argument for this Ground:
- Prior Art Mapping: This ground addressed claims requiring separate physical arbiters for the two ordering steps. Petitioner contended Guthrie teaches two distinct ordering functions: the baseline PCI rules and the additional PRT rules. While Guthrie does not explicitly require separate hardware, O'Connor teaches a high-speed, "starvation-free arbiter system" and discloses that using two-stage arbitration with separate arbiters is a known technique for improving access and efficiency in pipelined systems.
- Motivation to Combine (for §103 grounds): A POSITA would combine the teachings to improve the performance of Guthrie’s pipelined system. Since Guthrie already separates the ordering logic into two distinct functions (PCI and PRT), a POSITA would have been motivated to implement these functions using the separate hardware arbiters taught by O'Connor to gain the known efficiency benefits for such pipelined systems.
- Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because O'Connor explicitly applies its multi-arbiter scheme to a pipelined system, the same type of system disclosed in Guthrie.

Prior Art Relied Upon: Hyun (The Effective Buffer Architecture for Data Link Layer of PCI Express, 2004).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Hyun, which teaches an improved buffer architecture for PCI Express, discloses the claimed two-step ordering. Hyun's system adheres to standard PCI Express ordering rules for packets within the same "Traffic Class" (TC), which corresponds to the claimed "protocol-based ordering." Hyun then teaches an "efficient buffer management scheme" that introduces independent ordering rules for packets in different TCs to "increase performance and efficiency." This secondary ordering, which allows a higher-priority packet (e.g., TC1) to pass a lower-priority one (e.g., TC0), was mapped to the claimed "performance-based" ordering. The "control unit" in Hyun's architecture was identified as the second, performance-based arbiter.
- Motivation to Combine (for §103 grounds): Not applicable as this ground relies on a single reference.
- Expectation of Success (for §103 grounds): Not applicable.
Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) based on Hyun in view of Guthrie, arguing Guthrie's teachings would have motivated a POSITA to implement Hyun's two-step ordering functionality on the receiving side of a transaction.

"packet processor" (claim 1): Petitioner argued this term should be given its plain and ordinary meaning: "a processor that processes packets." This construction was advanced to counter an anticipated argument from the Patent Owner, based on a prior IPR, that the term should be narrowly construed to exclude conventional CPUs and require the merging of packet streams from multiple sources. Petitioner contended that neither the claims nor the specification supported such a narrow construction.

Petitioner argued against discretionary denial under §325(d) because the primary prior art references (Guthrie, Hyun, O'Connor) were never presented to or considered by the Examiner during prosecution, making the petition non-cumulative.
Petitioner argued against discretionary denial under Fintiv factors (§314(a)), asserting that the co-pending district court litigation was in its infancy with no trial date set, no significant investments made by the court or parties, and that the PTAB’s Final Written Decision would likely issue before any trial. Petitioner also stipulated that, if review is instituted, it would not pursue the same invalidity grounds in the district court, mitigating concerns of duplicative efforts.

Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’680 patent as unpatentable.