PTAB

IPR2021-01454

Google LLC v. Sonrai Memory Ltd

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multiprocessing Chip Utilizing Multiple Operating Systems
  • Brief Description: The ’014 patent discloses a multiprocessing system featuring multiple processors mounted on a single die. The system is designed to run multiple operating systems simultaneously from a connected memory, with different processors or groups of processors capable of executing different operating systems.

3. Grounds for Unpatentability

Ground 1: Obviousness over Asano and Joy - Claims 1-3, 5-9, 11-13, and 15-19 are obvious over Asano in view of Joy.

  • Prior Art Relied Upon: Asano (Application # 2001/0044817) and Joy (Patent 6,542,991).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Asano taught a multiprocessing computer system capable of running a plurality of operating systems from a connected memory. Asano’s system allocated different processors or groups of processors to different operating systems, which could be run simultaneously (e.g., one active, one standby). However, Asano did not explicitly disclose mounting its multiple processors on a single die. Joy was alleged to cure this deficiency by disclosing a processor architecture that "combines multiple processors on a single integrated circuit die" to augment efficiency, decrease latency, and accelerate context switching to nanosecond speeds. The combination of Asano's multi-OS system with Joy's single-die, fast-switching processor architecture allegedly rendered the limitations of the challenged claims obvious, including the simultaneous execution of multiple operating systems by processors on a single die.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Asano and Joy because both references addressed improving computer systems, particularly for server applications. A POSITA would have been motivated to implement Asano’s multi-OS system using Joy’s single-die multiprocessor architecture to gain Joy’s disclosed benefits, such as increased performance, reduced communication latency, and faster context switching. These benefits would be directly applicable and desirable for Asano’s system, which involves switching processors between different operating systems.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination involved applying the well-known concept of a single-chip multiprocessor (as taught by Joy and acknowledged as conventional in the ’014 patent itself) to Asano's system architecture. The integration was a straightforward application of known design principles with predictable results.

Ground 2: Obviousness over Asano and Babaian - Claims 1-3, 5-9, 11-13, and 15-19 are obvious over Asano in view of Babaian.

  • Prior Art Relied Upon: Asano (Application # 2001/0044817) and Babaian (Patent 7,143,401).
  • Core Argument for this Ground:
    • Prior Art Mapping: As in Ground 1, Asano provided the base system of multiple processors running multiple operating systems. Petitioner asserted that Babaian, like Joy, supplied the missing limitation of mounting processors on a single die. Babaian disclosed a "single chip multiprocessor system" designed to substantially increase performance through parallel execution. It further taught a method for the "flexible assignment of the idle processors for the execution of a program," allowing the system to dynamically form working configurations of processors for specific tasks. Petitioner argued that combining Asano's architecture with Babaian's single-chip, flexible-assignment multiprocessor rendered the challenged claims obvious.
    • Motivation to Combine: A POSITA would have been motivated to combine the teachings of Babaian with Asano’s system to achieve the performance increases and efficiencies associated with single-chip multiprocessors. Specifically, Babaian’s flexible assignment of processors would have been seen as an advantageous way to implement Asano’s allocation of processors to different operating systems. This combination would allow for quick and efficient reallocation of processing resources on a single die, improving upon the system disclosed in Asano while also reducing its physical size and increasing data exchange efficiency.
    • Expectation of Success: The combination was presented as a predictable integration of known technologies. A POSITA would have been skilled enough to configure Asano’s system with Babaian’s single-die architecture to achieve the foreseeable result of a more compact and higher-performance multi-OS system, with a high expectation of success.

4. Key Claim Construction Positions

  • Petitioner argued that several terms in means-plus-function format in claim 12 required construction under 35 U.S.C. § 112, ¶6.
    • "processor means": Petitioner proposed construing this term as a "chip multiprocessor having multiple processors mounted on a single die, or equivalents thereof," based on the corresponding structure disclosed in the ’014 patent’s specification.
    • "operating system means": Petitioner proposed construction as a "conventional operating system, such as WINDOWS NT, UNIX, and the like, or equivalents thereof."
    • "memory means": Petitioner proposed construction as "SRAM and/or DRAM on the same chip as one or more processors; SRAM and/or DRAM on separate chips connected to one or more processors; magnetic media, such as tape or disk; optical media, such as CD-ROM; or equivalents thereof."

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §314(a) or §325(d) was inappropriate. The petition contended that the Fintiv factors weighed in favor of institution.
    • Trial Date & Investment: No trial date had been set in the parallel district court litigation (Sonrai Memory Ltd. v. Google LLC, W.D. Tex.), and there had not been significant investment of resources by the court or parties in that case.
    • Overlap: Petitioner argued there was minimal overlap, as it had not yet served its invalidity contentions in the district court. Further, Petitioner stipulated that if the IPR were instituted, it would not pursue the same grounds in the district court litigation, a factor that strongly favors institution.
    • Other Factors: Petitioner asserted that it filed the petition promptly after receiving Patent Owner's infringement contentions and that the challenge raised meritorious issues based on prior art not considered during prosecution, serving the public interest.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-9, 11-13, and 15-19 of the ’014 patent as unpatentable.