PTAB

IPR2021-01487

Apple Inc v. Future Link Systems LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Circuit with Test Unit for Interconnect Testing
  • Brief Description: The ’108 patent discloses an alternative to traditional boundary scan (JTAG) testing for integrated circuits. The invention proposes using an on-chip "low-complexity memory" test unit to test interconnects, thereby avoiding the need for dedicated test pins that were allegedly incompatible with the standardized pin layouts of devices like SDRAMs.

3. Grounds for Unpatentability

Ground 1: Obviousness over Langford - Claims 1, 3, 6, and 11-13 are obvious over Langford.

  • Prior Art Relied Upon: Langford (Patent 5,115,435).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Langford, filed nearly a decade before the ’108 patent, addresses the same problem of performing boundary scan testing without requiring additional, dedicated test pins. Langford was alleged to disclose all elements of independent claims 1 and 11, including an electronic circuit with a main logic unit and a separate test unit (its boundary scan circuit). Langford’s circuit operates in distinct normal and test modes, where in test mode, the I/O nodes are logically disconnected from the main unit and connected to the test unit to test interconnects. Petitioner contended Langford’s test unit, which employs latch-based registers to store and serially shift test data, functions as the claimed "low complexity memory." Dependent claim limitations were also allegedly met, as Langford's registers are read/write registers (claim 3), and its output register includes XOR gates for signature generation (claim 6).
    • Motivation to Combine (for §103 grounds): This ground asserted obviousness based on Langford in view of the general knowledge of a person of ordinary skill in the art (POSITA), rather than a combination of references. Petitioner argued a POSITA would have readily recognized that Langford’s latch-based register architecture constituted a "low complexity memory" as that term is described and claimed in the ’108 patent.

Ground 2: Obviousness over Langford and Hong - Claim 6 is obvious over Langford in view of Hong.

  • Prior Art Relied Upon: Langford (Patent 5,115,435) and Hong (Patent 4,241,307).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative challenge specifically to claim 6, which requires the test unit to comprise a "combinatorial circuit implementing an XOR function." Petitioner asserted that Langford provides the foundational circuit with test/normal modes and a test unit connected to I/O nodes. Hong was cited for its disclosure of using a simple, multi-input Exclusive-OR (XOR) circuit to efficiently test interconnects between modules on a circuit card.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Hong’s efficient XOR testing method with Langford’s boundary scan system as a predictable improvement. Petitioner argued that Langford’s input register design was relatively complex and required significant hardware, whereas Hong taught a much simpler, cheaper, and more space-efficient single XOR gate to achieve the same goal of interconnect testing. Substituting Hong’s simpler XOR gate for Langford’s more complex input circuitry was presented as an obvious design choice to reduce cost, decrease testing time, and minimize the circuit's silicon footprint.
    • Expectation of Success (for §103 grounds): Petitioner argued a POSITA would have a high expectation of success because Langford already uses XOR circuits in its output register for signature analysis, demonstrating familiarity with the technology. Therefore, implementing a similar XOR circuit at the input side of the test unit, as taught by Hong, would be a straightforward and predictable modification.

4. Key Claim Construction Positions

  • "testing the interconnects": For the purposes of the petition, Petitioner proposed adopting the construction previously advanced by the Patent Owner in parallel district court litigation: "applying test data to one end of an interconnect and observing response data at the other end."
  • "low complexity memory": Petitioner applied a construction previously agreed upon by the Patent Owner in litigation: "memory that does not have to be put through a complex initialization process before it can be accessed and that has simple access protocols without dynamic restrictions." Petitioner argued that Langford’s latch-based registers met this construction.

5. Arguments Regarding Discretionary Denial

  • Petitioner presented extensive arguments urging the Board to decline discretionary denial under both General Plastic and Fintiv factors.
  • General Plastic Factors: Petitioner argued against denial for serial petitions by noting this was its first challenge to the ’108 patent. It distinguished its petition from a prior-filed IPR by another petitioner (AMD, IPR2021-01301) by highlighting its reliance on a different primary reference (Langford) and substantially different invalidity arguments.
  • Fintiv Factors: Petitioner argued that factors related to the parallel district court litigation weighed in favor of institution. The litigation was in its early stages, with minimal investment from the parties and no claim construction order issued. While a proposed trial date was close to the potential Final Written Decision (FWD) deadline, Petitioner cited statistics on frequent trial date slippage in the relevant district (W.D. Tex.). Critically, Petitioner stipulated that if the IPR were instituted, it would not pursue in district court the invalidity grounds that rely on the base reference asserted in the petition (Langford), mitigating concerns of duplicative efforts and inconsistent rulings.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 3, 6, and 11-13 of Patent 6,622,108 as unpatentable.