Apple Inc v. Future Link Systems LLC

1. Case Identification

• Case #: IPR2021-01488
• Patent #: 6,807,505
• Filed: September 28, 2021
• Petitioner(s): Apple Inc.
• Patent Owner(s): Future Link Systems, LLC
• Challenged Claims: 1, 6, and 8

2. Patent Overview

• Title: Electronic Circuit with Test Unit
• Brief Description: The ’505 patent discloses an electronic circuit, such as one including an SDRAM, with an integrated test unit for testing interconnects. The invention is presented as an alternative to conventional boundary scan (JTAG) testing, which requires dedicated test pins that are allegedly incompatible with the standardized pin layouts of devices like SDRAMs. The patent’s test unit uses a low-complexity memory or combinatorial logic to test address and data buses without needing the traditional JTAG architecture.

3. Grounds for Unpatentability

Ground 1: Claims 1, 6, and 8 are obvious over Hong in view of the knowledge of a POSITA.

• Prior Art Relied Upon: Hong (Patent 4,241,307) and the general knowledge of a Person of Ordinary Skill in the Art (POSITA).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hong, filed nearly two decades before the ’505 patent, discloses every element of the challenged claims. Hong teaches a "module interconnection testing scheme" for electronic modules mounted on a card. Each module in Hong contains a main unit ("logic circuits") for normal operation and a test unit comprising an "Exclusive-OR" (XOR) circuit. Hong explicitly describes switching between a "normal mode," where the logic circuits are connected to the input/output (I/O) pins to perform their intended function, and a "test mode," where the test unit is connected to the I/O pins to test the interconnects for "stuck at 1" or "stuck at 0" faults.
  • Petitioner mapped these disclosures directly to the challenged claims. For independent claim 1, Hong’s modules were asserted to be the claimed "electronic circuit," its logic circuits the "main unit," and its XOR circuitry the "test unit." Hong’s description of switching between modes based on a binary signal (1 for normal, 0 for test) applied to a control terminal (pin 12b) was argued to teach the claimed normal and test modes. Dependent claim 6, which specifies the test unit uses a combinatorial XOR circuit, was asserted to be directly taught by Hong’s XOR tree. Dependent claim 8, which adds a "test control node" to switch modes based on a signal value, was asserted to be taught by Hong's control terminal 12b.
  • Motivation to Combine: Petitioner contended that the combination was trivial, as Hong itself discloses a complete, integrated system that performs the claimed functions. The reliance on the "knowledge of a POSITA" was primarily to confirm that a skilled artisan would understand standard terminology (e.g., that Hong's "Exclusive-OR circuit" is a combinatorial circuit implementing an XOR function) and the fundamental operation of the disclosed components. Therefore, a POSITA seeking to test interconnects would have found it obvious to implement the system taught by Hong.
  • Expectation of Success: As Hong describes a fully functional and operational system for testing interconnections using the very architecture claimed, Petitioner argued a POSITA would have had a very high expectation of success in implementing its teachings.

4. Key Claim Construction Positions

• Petitioner proposed that the Board adopt the construction for the term "testing the interconnects" that the Patent Owner successfully advanced in a prior district court litigation.
• The proposed construction is "applying test data to one end of an interconnect and observing response data at the other end." Petitioner adopted this construction for the purposes of the IPR petition to demonstrate invalidity even under the Patent Owner's own preferred definition.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) based on the Fintiv factors would be inappropriate and that the Board should institute review.
• The core arguments were:
  • The parallel district court case was in its earliest stages, with minimal investment by the parties or the court. Key events like claim construction had not yet occurred.
  • While the proposed trial date was two months prior to the statutory deadline for a Final Written Decision (FWD), Petitioner argued that trial dates in the Western District of Texas are highly speculative and frequently slip, making reliance on the schedule improper.
  • To mitigate any concerns of inefficiency or overlap, Petitioner stipulated that, if the IPR is instituted, it will not pursue any invalidity ground in the district court litigation that relies on Hong.
  • Finally, Petitioner contended that the merits of the petition are exceptionally strong, which weighs heavily in favor of institution to correct the record for an erroneously issued patent.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 6, and 8 of the ’505 patent as unpatentable.