Microchip Technology Inc v. HD Silicon Solutions LLC

1. Case Identification

• Case #: IPR2021-01567
• Patent #: 7,810,002
• Filed: September 23, 2021
• Petitioner(s): Microchip Technology Inc.
• Patent Owner(s): HD Silicon Solutions LLC
• Challenged Claims: 1-6, 8, 9, 11, 12, and 15-19

2. Patent Overview

• Title: Providing Trusted Access to a JTAG Scan Interface in a Microprocessor
• Brief Description: The ’002 patent discloses a method and system for securing a scan chain architecture, such as a JTAG scan interface, in a microprocessor. The system disables the interface by default and uses a trusted software layer to perform an authentication operation before enabling access, thereby protecting sensitive data from unauthorized users during debugging.

3. Grounds for Unpatentability

Ground 1: Obviousness over Giles - Claims 1-6, 8, 9, 11, 12, and 15-19 are obvious over Giles.

• Prior Art Relied Upon: Giles (Patent 7,228,440).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Giles taught all limitations of the challenged claims. Giles disclosed a secure device with an Extended Joint Test Action Group (EJTAG) debug interface that can be disabled. The interface was disabled by default upon booting the secure processor. Giles’ boot read-only memory (ROM) code (the claimed "software layer") executed a challenge-response authentication procedure upon receiving authentication information via a UART interface. If the authentication was successful, the boot ROM code would set a register to enable the EJTAG probe, allowing access to the secure processor's resources.
  • Key Aspects: Petitioner contended that Giles’ "secure component 102" corresponded to the claimed "secure processor," its "boot ROM code 163" was the "software layer," and its "EJTAG interface" was the "scan interface." The method of disabling upon boot-up, authenticating via software, and subsequently enabling the interface directly mapped to the steps of independent claims 1 and 17 and the system of claim 11.

Ground 2: Obviousness over Moyer - Claims 1, 2, 5, 6, 8, 9, 11, 15-17, and 19 are obvious over Moyer.

• Prior Art Relied Upon: Moyer (Patent 7,248,069).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Moyer disclosed a method for providing security for debug circuitry, including a JTAG interface. Moyer described a system with multiple security states, including an an initial secure state where the debug interface was disabled (STATE B) and a state where access was granted after a proper authentication was performed (STATE C). Petitioner argued that Moyer’s "debug or emulation software" constituted the claimed "software layer," which was authorized to access the "protected functional circuitry" (the "secure processor"). The software layer received authentication information (e.g., passwords or keys) and, if valid, enabled the debug interface.
  • Key Aspects: Petitioner contended that transitioning between Moyer's security states via a hardware or software reset corresponded to "booting up" the processor and disabling the scan interface by default. The authentication process, which could be implemented using any combination of hardware and software, fulfilled the claim limitations of receiving, verifying, and allowing access based on authentication information.

Ground 3: Obviousness over Moyer in view of Giles - Claims 3, 4, 12, and 18 are obvious over Moyer in view of Giles.

• Prior Art Relied Upon: Moyer (Patent 7,248,069) and Giles (Patent 7,228,440).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addressed dependent claims requiring the specific use of an internal register to control the state of the scan interface. Petitioner argued that while Moyer taught the broader concept of enabling and disabling a debug interface based on security states, Giles provided the specific implementation detail of using an internal register (its Security Resource Control register) with specific flag bits (the EDIS flag) to control the interface state.
  • Motivation to Combine: Petitioner asserted a person of ordinary skill in the art (POSITA) would combine Moyer and Giles because both references addressed the same problem of securing debug ports on integrated circuits and were filed less than a year apart. A POSITA would have been motivated to implement Moyer's security state framework using the specific, well-defined register-based control mechanism disclosed in Giles to create a more robust and predictable security system.
  • Expectation of Success: The combination was argued to be a predictable integration of known hardware components and architectures, yielding no unexpected results.

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) based on the combination of Moyer and Giles for claims 1, 2, 5, 6, 8, 9, 11, 15-17, and 19, arguing that to the extent any element was missing from either reference alone, the combination rendered the claims obvious.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a), based on the Fintiv factors, was inappropriate. The core arguments were:
  • The estimated trial date in the parallel district court litigation was likely to slip past the statutory deadline for a Final Written Decision (FWD) in the inter partes review (IPR).
  • There had not been significant investment in the district court proceeding, as it was still in early stages before a claim construction ruling.
  • The petition presented a strong case for unpatentability, which weighed in favor of institution.

5. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-6, 8, 9, 11, 12, and 15-19 of Patent 7,810,002 as unpatentable.