Samsung Electronics Co Ltd v. Netlist Inc

1. Case Identification

• Case #: IPR2022-00064
• Patent #: 10,474,595
• Filed: October 15, 2021
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-24

2. Patent Overview

• Title: Memory Module Having An Open-Drain Output Pin For Parity Error In a First Mode and For Training Sequences In a Second Mode
• Brief Description: The ’595 patent describes a memory module that uses a single open-drain output pin for dual purposes. The pin is configured to signal parity errors to a memory controller during a first operational mode and to provide status information for training sequences during a second, distinct mode, such as system initialization.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hazelzet and JEDEC - Claims 1-24

• Prior Art Relied Upon: Hazelzet (Application # 2008/0098277) and JEDEC (a 2009 LRDIMM Memory Initialization Chapter Proposal).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hazelzet taught a memory module system with an ECC/Parity register using a shared open-drain output pin (the UE 121 pin) to signal different types of errors (uncorrectable or parity) depending on its operating mode. JEDEC was asserted to teach using the same type of open-drain error pin (ERROUT#) on a memory module to signal the completion of memory buffer training sequences during an initialization mode, during which no normal memory read/write operations occur. Petitioner contended the combination of these references disclosed all elements of the challenged claims.
  • Motivation to Combine: A POSITA would combine these references to improve the reliability of Hazelzet’s system by adding the training functionality taught by JEDEC. The combination represented a natural design evolution, upgrading Hazelzet's Registered DIMM (RDIMM) to the more advanced Load-Reduced DIMM (LRDIMM) of JEDEC, which required such training. Reusing Hazelzet's existing open-drain pin for this new function was an efficient and known technique for saving limited pin resources.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success, as combining known training sequences with a memory module and using an open-drain pin for status signaling were all well-understood techniques at the time.

Ground 2: Obviousness over Hazelzet and Buchmann - Claims 1-24

• Prior Art Relied Upon: Hazelzet (Application # 2008/0098277) and Buchmann (Patent 8,139,430).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative to Ground 1, with Buchmann substituting for JEDEC. Petitioner asserted that Buchmann, like JEDEC, taught a memory module with a buffer that performs training sequences (e.g., TS0, TS3) during power-on initialization. Buchmann also taught generating notification signals (e.g., "TS_done") to indicate the status of these training sequences to the memory controller.
  • Motivation to Combine: The motivation was analogous to the JEDEC combination. Buchmann's disclosed "training phase" offered "improved control data exchange" and "reliable communication," which would have motivated a POSITA to incorporate it into Hazelzet's system to improve its reliability. Buchmann also disclosed a buffer for data, address, and command signals, providing a known technique to improve the performance and capacity of Hazelzet’s module.
  • Expectation of Success: Implementing Buchmann's training on Hazelzet's hardware platform was a predictable application of known technologies with a high likelihood of success.

Ground 3: Obviousness over Hazelzet/JEDEC/Buchmann and Kim - Claims 3-7, 12-14, 20, 22, and 23

• Prior Art Relied Upon: The combinations from Grounds 1 or 2, further combined with Kim (Patent 8,359,521).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that if the primary combinations were found deficient in teaching the specific notification circuitry, Kim cured the deficiency. Kim explicitly taught the detailed circuitry for using a single open-drain output for multiple purposes, including a logic element (an OR gate) to select which signal (e.g., parity error, ECC error) drives the gate of the open-drain transistor based on the module's current mode.
  • Motivation to Combine: A POSITA seeking to implement the combined functionality of Hazelzet and JEDEC/Buchmann would have been motivated to consult Kim for its detailed, reliable, and pin-saving circuit design. As Kim was assigned to the same company as Hazelzet and addressed highly analogous problems, Petitioner argued it was a natural and obvious reference to consider for implementation details.
  • Expectation of Success: Using Kim's logic gate and transistor configuration to arbitrate between the parity error signal from Hazelzet and the training status signal from JEDEC or Buchmann was a straightforward application of basic circuit design principles to achieve a predictable result.

4. Key Claim Construction Positions

• Petitioner argued for constructions of several key terms that were critical to its invalidity analysis.
• "normal memory read or write operations": Petitioner contended this term should be construed as standard operations for reading from or writing to memory devices, regardless of the module's overall operating mode. This construction supports the argument that the prior art training modes, which did not involve such controller-initiated memory access, meet the negative claim limitation that the module "is not accessed... for normal memory read or write operations" in the second (training) mode.
• "training sequence": Petitioner proposed the construction "a set of operations occurring in a particular order and used for training." This broad construction was argued to encompass the training operations disclosed in the JEDEC and Buchmann references.

5. Key Technical Contentions (Beyond Claim Construction)

• Effective Filing Date: A central contention was that the ’595 patent was not entitled to its claimed June 2009 priority date and was instead limited to its June 2010 filing date. Petitioner argued the provisional application failed to provide written description support for key limitations added later, particularly the negative limitation that "normal memory read or write operations" do not occur during the training mode. This argument, if successful, establishes the JEDEC proposal (a November 2009 publication) as prior art.

6. Arguments Regarding Discretionary Denial

• Petitioner argued extensively against discretionary denial under 35 U.S.C. §314(a) and §325(d). The core argument was that while the same grounds were asserted in a prior IPR (IPR2020-01042), that case was terminated post-institution due to a settlement. Petitioner contended it was not a party to that prior IPR and had a legitimate reason for not joining, as it held a license to the patent at that time. Petitioner asserted that subsequent litigation by the Patent Owner challenging that license created the changed circumstances that necessitated the current petition.

7. Relief Requested

• Petitioner requested that the Board institute an inter partes review and cancel claims 1-24 of Patent 10,474,595 as unpatentable.