Hewlett Packard Enterprises Co v. Intellectual Ventures II LLC

1. Case Identification

• Case #: IPR2022-00116
• Patent #: 7,882,320
• Filed: October 29, 2021
• Petitioner(s): Hewlett Packard Enterprise Co.
• Patent Owner(s): Intellectual Ventures II LLC
• Challenged Claims: 1-3, 5-8

2. Patent Overview

• Title: Data Storage Device with Distributive Architecture
• Brief Description: The ’320 patent describes a data storage device with a "distributive architecture" designed to improve scalability and performance for enterprise applications. The architecture features multiple microprocessor units, each with a dedicated portion of RAM, and dedicated bus connections to non-volatile flash memory configurations, managed by a central dataflow controller.

3. Grounds for Unpatentability

Ground 1: Claims 1-3 and 5-8 are obvious over Nakamura in view of Benhase

• Prior Art Relied Upon: Nakamura (Patent 7,464,221) and Benhase (Patent 7,260,679).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nakamura disclosed a distributed storage system with the core architectural elements of claim 1: a host interface, multiple microprocessor units (FM control units), each with access to dedicated portions of volatile cache memory (RAM), and dedicated bus connections to non-volatile memory configurations (FM devices). However, Nakamura's method for destaging data (moving data from cache to non-volatile memory) focused on what data to move (using a Least-Recently-Used algorithm) rather than when to move it, potentially allowing the cache to become full. Benhase was argued to supply the missing element by teaching a destaging process triggered when the amount of valid data in a cache meets or exceeds a preset threshold (e.g., 90% of capacity). The combination of Nakamura’s architecture and Benhase’s threshold-based destaging allegedly rendered the claims obvious.
  • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Nakamura and Benhase to improve the performance and stability of Nakamura's system. A POSITA would have recognized that allowing a write-back cache to become completely full before destaging, as implied in Nakamura, creates a risk of cache overflow and performance bottlenecks. Benhase provided a well-known and direct solution to this problem by initiating destaging before the cache is full. A POSITA would therefore have been motivated to incorporate Benhase’s preset threshold technique into Nakamura’s system to prevent overflow and ensure consistent performance, a key goal for large-scale storage systems.
  • Expectation of Success: Petitioner asserted a POSITA would have had a reasonable expectation of success because the references are analogous art, both concerning distributed data storage systems with write-back caches. The proposed modification was described as straightforward, requiring only the addition of a threshold value to Nakamura’s existing data structures that already tracked cache usage, which would then trigger the existing destaging mechanism.

Ground 2: Claims 1-3 and 5-8 are obvious over Mizushima in view of Hu

• Prior Art Relied Upon: Mizushima (Patent 7,761,655) and Hu ("RAPID Cache—A Reliable and Inexpensive Write Cache for High Performance Storage Systems," an IEEE journal article from March 2002).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mizushima disclosed a distributed storage architecture with multiple microprocessor units (storage adapters), each having a dedicated volatile DRAM cache and dedicated bus connections to parallel flash memory modules. Mizushima's system initiated destaging when a write request was received and there was no "empty entry" in the cache. To address this inefficient "full-cache" destaging trigger, Petitioner asserted that Hu taught a superior and well-known "high-low water-mark" algorithm. Hu disclosed initiating destaging when the number of "dirty blocks" (valid data) in the cache exceeded a high water-mark (e.g., 70% of capacity), thus creating free space before it is critically needed.
  • Motivation to Combine: The motivation to combine Mizushima and Hu, as argued by Petitioner, stemmed from the need to solve the cache overflow problem inherent in Mizushima's design. Mizushima itself acknowledged that system performance could become "unstable" if available cache capacity became too low. Hu expressly addressed this exact issue by using a high water-mark threshold to proactively manage cache space and prevent performance degradation. A POSITA seeking to build a robust system based on Mizushima's architecture would have been motivated to implement the well-documented and effective water-mark algorithm from Hu to ensure stable, guaranteed performance.
  • Expectation of Success: Petitioner claimed a reasonable expectation of success because the proposed combination involved applying a standard cache management algorithm (Hu) to a known system architecture (Mizushima) to achieve a predictable improvement. A POSITA could have readily implemented Hu's threshold by storing the value in Mizushima's shared memory and executing background "destaging threads" on its existing channel adapters, which already performed cache management tasks.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv was not warranted. The parallel district court proceeding was in its early stages, with significant discovery and claim construction events yet to occur.
• Crucially, Petitioner stipulated that it would not pursue the same invalidity grounds in the district court proceeding, which it argued eliminated the issue overlap that is central to the Fintiv analysis.
• Petitioner also asserted that denial under 35 U.S.C. §325(d) was inappropriate because the primary references (Nakamura, Benhase, Mizushima, and Hu) were not considered during the original prosecution of the ’320 patent.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-3 and 5-8 of the ’320 patent as unpatentable.