PTAB

IPR2022-00208

Apple Inc v. Future Link Systems LLC'S

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Circuit Arrangement and Method for Interfacing Functional Blocks
  • Brief Description: The ’804 patent discloses a circuit arrangement for interconnecting multiple “functional blocks” (e.g., microprocessors, memory controllers) together within a single integrated circuit device. The arrangement utilizes an interface controller and “concurrent serial interconnects” capable of routing separate serial command, data, and clock signals between the functional blocks to support high-speed data throughput.

3. Grounds for Unpatentability

Ground 1: Obviousness over Fu in view of Starke - Claims 1-5, 8-10, 14, 17, 21-22, and 40 are obvious over Fu in view of Starke.

  • Prior Art Relied Upon: Fu (Patent 6,065,077) and Starke (Patent 5,889,947).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Fu taught a symmetric multiprocessing (SMP) system that meets nearly all limitations of the challenged claims. Fu’s system used a Flow Control Unit (FCU) to interconnect multiple devices (processors, memories) via dedicated point-to-point channels. Crucially, these channels comprised separate clock, control (command), and data lines, analogous to the ’804 patent’s claimed interconnects. The FCU functions as the claimed interface controller, selectively coupling devices to establish logical communication channels. Petitioner contended that Fu’s primary missing limitation was the explicit disclosure of locating all functional blocks and the interconnect architecture on a single integrated circuit chip. Starke, which addresses a similar SMP system, was argued to supply this missing element by expressly teaching the implementation of multiple processors on a “single-chip integrated circuit” to achieve higher bandwidth and lower latency.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Fu’s architecture with Starke’s single-chip implementation to achieve the well-understood benefits that Starke explicitly taught. These benefits included increased data bandwidth, decreased latency, cost-effectiveness, and efficiency, which were consistent with the general market trend at the time toward system-on-chip (SoC) integration. The combination was presented as a predictable application of known design principles to improve Fu's existing system.
    • Expectation of Success: Petitioner asserted a POSITA would have had a reasonable expectation of success in this combination. Architectures incorporating multiple processors and modules on a single chip were well-known prior to the ’804 patent’s priority date. Modifying Fu’s system to be a single-chip implementation would have involved applying standard manufacturing techniques to a known architecture to predictably yield a more compact and efficient system.

4. Key Claim Construction Positions

  • "serial port": This term was identified as central to the invalidity argument. Petitioner argued for adopting the construction that the Patent Owner previously advanced in parallel district court litigation: "a port that transfers bits, characters, or data units sequentially." This construction is broad and does not limit "serial" transmissions to a single wire; it explicitly encompasses the sequential transfer of multi-bit data packets across multiple wires.
  • Importance: Adopting this construction was critical to Petitioner's case because Fu’s system communicates via sequential 16-bit packets transmitted over a multi-wire bus. While this might not meet a narrow "one bit at a time over one wire" definition of serial, Petitioner argued it squarely satisfies the Patent Owner’s own broader construction of "sequential data transfer," thereby allowing Fu to teach the "serial port" limitation.

5. Arguments Regarding Discretionary Denial

  • Petitioner presented extensive arguments that discretionary denial under 35 U.S.C. §314(a) based on the Fintiv factors would be inappropriate. The core arguments were:
    • Early Stage of Litigation: The parallel district court case in the Western District of Texas was in its early stages, with minimal investment by the court and parties and no substantive orders issued. A Markman hearing had not yet occurred.
    • Unreliable Trial Date: Petitioner argued the scheduled trial date was speculative and highly likely to be delayed, citing statistics on frequent trial slippage in the Waco Division of WDTX, which undermines a key Fintiv factor.
    • Stipulation to Reduce Overlap: To mitigate concerns of duplicative efforts, Petitioner stipulated that if the IPR is instituted, it will not pursue in the district court any invalidity grounds that rely on the Fu reference.
    • Strong Merits: The petition asserted that the strength of the obviousness grounds weighed heavily in favor of institution to promote patent quality and system integrity.
    • Challenge to Fintiv Framework: Petitioner also argued that the Fintiv framework itself exceeds the USPTO Director’s statutory authority, is arbitrary and capricious, and was improperly adopted without notice-and-comment rulemaking.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-5, 8-10, 14, 17, 21-22, and 40 of the ’804 patent as unpatentable.