Apple Inc v. Future Link Systems LLC

1. Case Identification

• Case #: IPR2022-00209
• Patent #: 7,917,680
• Filed: November 18, 2021
• Petitioner(s): Apple Inc.
• Patent Owner(s): Future Link Systems, LLC
• Challenged Claims: 1-10 and 12-20

2. Patent Overview

• Title: Packet Ordering in a Packet-Based Communication System
• Brief Description: The ’680 patent discloses a method for controlling the order of data packets in a communication system like PCI Express. The alleged invention is a two-step process that first applies protocol-based ordering rules and then applies a separate, second performance-based ordering to the packets.

3. Grounds for Unpatentability

Ground 1: Claims 1-10 and 12-20 are obvious over Budruk in view of the knowledge of a POSITA.

• Prior Art Relied Upon:
  • Budruk ("PCI Express System Architecture," a 2003 book describing the PCI Express 1.0a specification)
• Core Argument for this Ground:
  • Petitioner argued that the ’680 patent’s purported invention—a two-step packet ordering process—was not novel but was, in fact, an integral part of the very PCI Express standard the patent claims to improve. The Petitioner asserted that the reference, Budruk, explicitly describes this two-step process, and the patent owner simply ignored this existing functionality and claimed it as its own invention.
  • Prior Art Mapping:
    • Petitioner contended that Budruk teaches every limitation of the challenged claims. The first claimed step, "protocol-based ordering," was mapped to Budruk’s description of PCI Express’s fundamental ordering rules, flow control, and transaction-type buffers (Posted, Non-Posted, Completion). This process determines which packets are valid for transmission based on protocol compliance.
    • The second claimed step, "performance-based ordering," was mapped to Budruk’s detailed explanation of Virtual Channel (VC) arbitration. Petitioner argued that VC arbitration is a performance-based mechanism designed to improve Quality of Service (QoS) by selecting which "valid" packets to transmit from various buffers based on priority schemes (e.g., weighted round-robin). This arbitration occurs after the protocol-based rules have been applied, directly corresponding to the patent’s claimed two-step structure.
  • Motivation to Combine (for §103 grounds):
    • The ground was based on a single reference, Budruk, in view of a POSITA's knowledge. Petitioner argued a POSITA would have recognized that the two distinct ordering phases described in Budruk (protocol-based flow control and performance-based VC arbitration) were standard components of the PCI Express architecture. A POSITA would have been motivated to use these known techniques together as described in the standard to achieve the predictable result of efficient and prioritized packet transmission.
  • Expectation of Success:
    • As Budruk describes the established and functioning PCI Express 1.0a standard, a POSITA would have had a 100% expectation of success in implementing the described protocol-based and performance-based ordering steps.

4. Key Claim Construction Positions

• Petitioner stated its willingness to adopt the Patent Owner’s proposed plain and ordinary meaning constructions for the purpose of the IPR proceeding to enhance judicial efficiency.
• Petitioner also noted prior constructions from related litigation for key terms, arguing the claims remain obvious even under those constructions.
  • "generating a performance-based communications order": Construed as "generating a communications order further based on desirable performance characteristics."
  • Petitioner argued Budruk’s disclosure of VC arbitration as a Quality of Service (QoS) feature that orders packets based on priority directly satisfies this construction, as optimizing QoS is a "desirable performance characteristic."

5. Key Technical Contentions (Beyond Claim Construction)

• Petitioner’s central technical contention was that the PCI Express standard, as detailed in Budruk, inherently includes the patent’s allegedly novel two-step ordering process. The core of this argument rested on the technical characterization of VC arbitration not as part of the protocol-based rules, but as a distinct, subsequent performance-based ordering step. Petitioner asserted that the patent’s failure to acknowledge this fundamental aspect of the PCI Express architecture is the fatal flaw in its claim to novelty.

6. Arguments Regarding Discretionary Denial

• Petitioner presented extensive arguments that discretionary denial under both 35 U.S.C. §325(d) (General Plastic factors) and §314(a) (Fintiv factors) would be inappropriate.
• Serial Petitions (General Plastic): Petitioner argued that it was a first-time challenger to the ’680 patent. It further contended that its sole ground, relying entirely on Budruk’s description of the unmodified PCI Express standard, was non-cumulative of grounds in prior IPRs against the patent. Those prior challenges were argued to rely on different prior art (e.g., Guthrie, a precursor PCI protocol) or on proposed modifications to the PCI Express standard, making the instant petition distinct.
• Parallel Litigation (Fintiv): Petitioner argued the factors strongly favored institution. It asserted that the parallel district court litigation was in its nascent stages with minimal investment from the parties or the court. Petitioner highlighted the statistical unreliability of early trial dates in the Western District of Texas and stipulated that, if the IPR were instituted, it would not pursue any invalidity grounds in district court based on Budruk, thereby mitigating concerns of duplicative efforts.

7. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-10 and 12-20 of the ’680 patent as unpatentable.