PTAB

IPR2022-00236

Micron Technology Inc v. Netlist Inc

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Timing Control
  • Brief Description: The ’035 patent relates to computer memory modules that include multiple memory chips, data buffers, and a module control device. The technology is directed at solving signal timing variations caused by different propagation delays from unbalanced wire lengths by using logic within the data buffers to obtain timing information from one type of memory operation (e.g., a write) and use it to control the timing of a subsequent, different memory operation (e.g., a read).

3. Grounds for Unpatentability

Ground 1: Obviousness over Osanai and Tokuhiro - Claims 1-2, 6, 10-13, and 21-22 are obvious over Osanai in view of Tokuhiro.

  • Prior Art Relied Upon: Osanai (Application # 2010/0312925) and Tokuhiro (Patent 8,020,022).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Osanai discloses a Load Reduced Memory Module (LRDIMM) that teaches most of the structural elements of the challenged claims, including a module board with memory devices, a central module control device, and data buffers distributed lengthwise. Osanai explicitly recognized the problem of differing propagation delays due to component spacing and disclosed using read and write leveling circuits within its data buffers to make timing adjustments. However, Petitioner contended Osanai does not expressly teach the core inventive concept: obtaining timing information from a second memory operation (a write) performed prior to a first memory operation (a read) to control the timing of the first operation. Petitioner asserted that Tokuhiro supplies this missing element by teaching the exact same concept—calculating a delay time for read operations based on timing information obtained from a prior write leveling operation to solve the same propagation delay problem.
    • Motivation to Combine: A POSITA would combine Tokuhiro’s timing compensation technique with Osanai's well-established LRDIMM architecture to solve the known problem of propagation delays more efficiently. Petitioner identified several motivations, including improving system performance by reducing the steps needed to determine read delay, reducing power consumption and circuit area (an express teaching of Tokuhiro), and improving overall signal fidelity. The combination represented the application of a known, superior technique to improve a similar, known device.
    • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved implementing a known timing control method (Tokuhiro) into a standard memory architecture (Osanai) to achieve the predictable result of improved timing compensation.

Ground 2: Obviousness over Takefman and Tokuhiro - Claims 1-2, 6, 12-13, and 21 are obvious over Takefman in view of Tokuhiro.

  • Prior Art Relied Upon: Takefman (Patent 8,713,379) and Tokuhiro (Patent 8,020,022).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner presented Takefman as an alternative base reference to Osanai. Takefman discloses a "TeraDIMM" memory module architecture with DRAM memory devices, data buffer devices ("Bolt devices"), and central control circuitry ("Rush"). Takefman also addresses signal timing issues arising from different component distances by using per-lane delay compensation circuits. Similar to the argument in Ground 1, Petitioner asserted that Takefman teaches the foundational buffered memory module structure but lacks the specific claimed method of using timing information from a prior write operation to control a subsequent read operation. Tokuhiro was again relied upon to teach this specific technique.
    • Motivation to Combine: A POSITA would combine Tokuhiro’s technique with Takefman's architecture for reasons analogous to those in Ground 1. Both Takefman and Tokuhiro address the same field and problems. A POSITA would have recognized the benefits of incorporating Tokuhiro's more efficient, power-saving timing solution into the Takefman module to improve its performance and solve the known issue of propagation delay. The modification was argued to be a predictable design choice to improve a known device.
    • Expectation of Success: The combination of Takefman and Tokuhiro would have been straightforward for a POSITA, yielding the predictable outcome of enhanced timing control in a buffered memory module.

  • Additional Grounds: Petitioner asserted a third ground that claims 1-2, 6, 12-13, and 21 are obvious over Takefman and Tokuhiro in further view of Osanai, using Osanai to demonstrate that certain modifications to Takefman's system would have been well-known and obvious to a POSITA.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate due to a parallel district court proceeding. It contended that a stipulation filed in the district court—promising not to pursue the same invalidity grounds raised in the IPR—mitigates concerns of duplicative efforts. Petitioner also noted the parallel litigation was in an early stage with no trial date set, and that the IPR petition presented strong merits.
  • Petitioner further argued against denial under §325(d) based on a prior IPR on a parent patent (’632 patent). It asserted that denial was unwarranted because the present petition involves a different petitioner, challenges a different patent with different claims, and relies on new prior art and expert testimony not previously considered by the Board.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-2, 6, 10-13, and 21-22 of the ’035 patent as unpatentable.