Samsung Electronics Co Ltd v. Sonrai Memory Ltd

1. Case Identification

• Case #: IPR2022-00306
• Patent #: 7,325,733
• Filed: December 10, 2021
• Petitioner(s): Samsung Electronics Co., Ltd., and Samsung Electronics America, Inc.
• Patent Owner(s): Sonrai Memory Ltd.
• Challenged Claims: 1-3, 5-7, 9, 11-15, 17-18, 20-23, and 25

2. Patent Overview

• Title: System and Method for Electrically Disconnecting a USB Device
• Brief Description: The ’733 patent discloses a power-saving method for Universal Serial Bus (USB) devices. The technology achieves an "electrical disconnect" of an inactive device from its host controller, without physical unplugging, by manipulating the device's data lines to create an electrical state that the host interprets as a physical disconnection per the USB standard.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 5, 7, 9, 11, 13-15, 17, 20, 22-23, and 25 are obvious over Cohen in view of USB 2.0.

• Prior Art Relied Upon: Cohen (Application # 2002/0138776) and USB 2.0 (“Universal Serial Bus Specification,” Revision 2.0).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Cohen discloses a USB system where a hub electrically disconnects from the host controller to conserve power when it becomes inactive (i.e., no devices are attached to its downstream ports). Cohen achieves this by using a Field-Effect Transistor (FET) to logically decouple the hub from the host, which electrically removes the pull-up resistor from the D+ data line. According to the USB 2.0 standard, this action creates a "Single-Ended Zero" (SE0) state on the data lines, which a host controller is required to interpret as a physical disconnection. This directly maps to the core limitations of independent claim 1, which requires an electrical disconnection that creates an "appearance to the host controller that the device is not coupled" to it.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Cohen with the USB 2.0 standard because Cohen explicitly discloses a USB system. The USB 2.0 specification was the operative industry standard at the time and would have been a necessary reference for implementing or understanding any such USB system to ensure compliance and proper functionality.
  • Expectation of Success: A POSITA would have a high expectation of success, as combining a description of a USB system with its governing standard is a routine and predictable design process.

Ground 2: Claims 6 and 18 are obvious over Cohen, USB 2.0, and Tornai.

• Prior Art Relied Upon: Cohen (Application # 2002/0138776), USB 2.0, and Tornai (Patent 5,408,668).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the Cohen/USB 2.0 combination to address the additional limitation in dependent claims 6 and 18, which require disconnection to occur if the device has "not been used in a specified amount of time." Petitioner asserted that Tornai teaches a power management system that uses a timer to verify that a peripheral device is truly inactive before disconnecting it from power. This prevents premature disconnection if a user is merely swapping devices, thereby avoiding unnecessary system disruption.
  • Motivation to Combine: A POSITA would be motivated to incorporate Tornai's timer-based approach into Cohen's system to improve its robustness and user experience. Using a timer to confirm inactivity is a common-sense design choice that prevents the system from disconnecting a device that is only momentarily idle, which would otherwise require a disruptive re-enumeration process upon reconnection.
  • Expectation of Success: A POSITA would have a high expectation of success in adding a timer function, as it is a simple and well-known technique in power management. The necessary hardware for monitoring line activity already exists in standard USB hubs, making the modification a predictable programming task.

Ground 3: Claims 1-3, 7, 9, 11-15, and 20-23 are obvious over Maemura in view of USB 2.0 and/or USB 1.0.

• Prior Art Relied Upon: Maemura (Patent 6,076,119), USB 2.0, and/or USB 1.0 (“Universal Serial Bus Specification,” Revision 1.0).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Maemura provides a strong alternative primary reference. Maemura explicitly discloses a power-saving system for an "inoperative" USB device. It teaches using a switching circuit to disconnect the pull-up resistor on the D+ or D- line from its power source. This action causes the voltage on the data lines to drop, creating the same SE0 disconnect condition defined in the USB standards. The host controller then perceives the device as physically disconnected, allowing the host processor to enter a low-power state. Maemura further discloses tri-stating the data lines to reduce power consumption, mapping to claim 12.
  • Motivation to Combine: A POSITA would combine Maemura with the USB 1.0 or 2.0 standard because Maemura explicitly states its invention operates "according to the USB...standard." A POSITA would naturally consult the relevant standard to understand the specific electrical states, protocols, and implementation details of the system Maemura describes.
  • Expectation of Success: A POSITA would have a high expectation of success because Maemura's system is expressly designed for USB compliance, making its combination with the official USB specification a straightforward and predictable engineering exercise.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise discretionary denial under 35 U.S.C. §325(d) or the Fintiv factors.
• Under §325(d), Petitioner asserted that the primary references of Maemura and Tornai, as well as the USB specifications, were never considered by the examiner during the original prosecution. Furthermore, the specific combinations of prior art presented in the petition are new and were not before the Patent Office.
• Regarding Fintiv, Petitioner argued that the petition presents overwhelming arguments for unpatentability, weighing in favor of institution. It was also noted that the parallel ITC proceeding cannot invalidate a patent, and this petition challenges several claims (e.g., 5, 12, 17, 21, 25) not at issue in the ITC. To further avoid overlap, Petitioner stipulated that if the IPR is instituted, it will not pursue the same grounds or primary references in the ITC.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-7, 9, 11-15, 17-18, 20-23, and 25 of the ’733 patent as unpatentable.