PTAB

IPR2022-00307

Samsung Electronics Co Ltd v. MyPAQ Holdings Ltd Transpacific IP Group Ltd

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1. Case Identification

2. Patent Overview

  • Title: Circuit Arrangement for a Switch-Mode Power Supply
  • Brief Description: The ’399 patent discloses a circuit arrangement for a switch-mode power supply (SMPS) where multiple primary-sided active components (e.g., control circuit, switching transistor, diodes) are integrated into a single shared housing. The stated goal is to save board space and improve heat dissipation through specific leadframe configurations.

3. Grounds for Unpatentability

Ground 1: Anticipation over Zverev - Claims 1-3, 5, 10, and 13 are anticipated by Zverev under 35 U.S.C. §102.

  • Prior Art Relied Upon: Zverev (German Application # DE10043485A1).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Zverev disclosed every element of the challenged claims. Zverev taught an SMPS with a control circuit (AS) on a first semiconductor chip and a primary-sided switch (T1) plus additional active components (semiconductor switch T2, sense MOSFET T3) integrated on a second semiconductor chip. Critically, Zverev taught that these two separate chips are arranged on a shared lead frame (a circuit carrier) and fitted into a single package (a shared housing), directly mapping to the limitations of independent claims 1 and 13.
    • Key Aspects: Petitioner contended Zverev’s disclosure of integrating the additional components (T2, T3) monolithically onto the same chip as the primary switch (T1) anticipated claim 10. Furthermore, the package depicted in Zverev’s Figure 5, with leads pointing downward for insertion into a PCB, was argued to be a "wired housing" compatible with through-hole technology, thus anticipating claim 3.

Ground 2: Obviousness over Liaw in view of Nam - Claims 1-6, 10, and 13 are obvious over Liaw in view of Nam under 35 U.S.C. §103.

  • Prior Art Relied Upon: Liaw (Patent 6,259,618) and Nam (Application # 2003/0102489).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Liaw disclosed a "power chip set" for an SMPS comprising a control unit on a first chip and a high-voltage chip containing the primary-sided switch and other active components. Liaw taught packaging this two-chip set "into a power module." Nam disclosed a specific multi-chip package structure using a lead frame as a shared circuit carrier, designed to mount a control IC and a separate high-voltage transistor chip next to each other while ensuring proper electrical insulation between them using insulating adhesive tape.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to implement Liaw’s two-chip SMPS circuit using Nam’s well-suited and cost-effective multi-chip packaging technology. Nam’s package was designed for components similar to Liaw’s and provided a known, predictable method for co-packaging them.
    • Expectation of Success: A POSITA would have had a high expectation of success because Nam’s package was designed for standard manufacturing processes and could be configured as a Dual In-Line (DIP) package for through-hole mounting (addressing claim 3) or a Small Outline (SO) package for surface-mounting (addressing claim 4). Nam’s lead frame also provided a large metal chip pad that functions as a cooling area, addressing claim 6.

Ground 3: Obviousness over Zverev in view of Shiraishi - Claims 4 and 6 are obvious over Zverev in view of Shiraishi under 35 U.S.C. §103.

  • Prior Art Relied Upon: Zverev (German Application # DE10043485A1) and Shiraishi (Application # 2004/0227547).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground used Zverev’s multi-chip SMPS package as a baseline. Shiraishi taught techniques for improving thermal dissipation in SMPS packages, specifically by exposing the back surface of the lead frame to create a thermal path to the PCB. Shiraishi also disclosed using this technique with surface-mount packages to facilitate close thermal coupling to the PCB.
    • Motivation to Combine: A POSITA would have been motivated to modify Zverev’s package with Shiraishi’s well-known heat dissipation technique to improve the thermal performance of the SMPS, a common design goal. Applying Shiraishi's teachings to Zverev's package would involve exposing the lead frame and utilizing surface-mount leads.
    • Expectation of Success: The combination was presented as the application of a known technique (Shiraishi's thermal management) to a similar device (Zverev's SMPS package) to yield a predictable result (improved heat dissipation). This modification would result in a surface-mountable housing (claim 4) where the exposed metal lead frame serves as a cooling area (claim 6).

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Zverev and Lacap (Patent 5,939,781); Liaw and Lin (Patent 5,491,360); and Liaw, Lin, and Shiraishi, which relied on similar principles of combining known packaging and thermal management techniques.

4. Key Claim Construction Positions

  • "active ... components" (claims 1, 13): Petitioner proposed this term be construed to mean "non-passive components including transistors, diodes, and integrated circuits (ICs) for pulse width modulation." This construction was based on examples provided in the ’399 patent’s specification and was used to map components from the prior art like secondary switches and sense transistors to this claim limitation.
  • "wired housing" (claim 3): Petitioner proposed this term be construed as "housing compatible with conventional through-hole technology." This construction was based on the specification's contrast between "wired housing" for Through Hole Technology (THT) and other housings for Surface Mount Technology (SMT).

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was not warranted. It asserted that the petition was filed promptly after receiving infringement contentions in a parallel district court case, with the district court trial date scheduled well after the deadline for a Final Written Decision (FWD) in the IPR. Petitioner also stipulated that it would not pursue the same invalidity grounds in the district court if the IPR were instituted.
  • Petitioner also argued against denial under §325(d), noting that none of the prior art references relied upon in the petition were considered by the Examiner during the original prosecution of the ’399 patent.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-6, 10, and 13 of the ’399 patent as unpatentable.