Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2022-00479
• Patent #: 7,523,373
• Filed: January 26, 2022
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-13, 15-16

2. Patent Overview

• Title: Minimum Memory Operating Voltage Technique
• Brief Description: The ’373 patent discloses a method for managing power in an integrated circuit (IC) containing a memory and a functional circuit (e.g., a processor). The method involves testing the IC to determine the memory’s minimum operating voltage, storing this value in non-volatile memory, and using a power supply selector to ensure the memory always receives a voltage at or above this minimum, even if the voltage supplied to the functional circuit drops below it for power-saving purposes.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harris, Abadeer, and Zhang - Claims 1-7, 9-11, 13, and 15-16 are obvious over Harris in view of Abadeer and Zhang.

• Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), and Zhang (Application # 2003/0122429).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of these references teaches all limitations of the challenged claims. Harris was asserted to teach a data processing system with a memory and a CPU, where a switching circuit selects between two different supply voltages (VDD and Vstby) for the memory. This switch is triggered when the primary voltage (VDD) falls below a "set level or threshold" to prevent memory data loss. Abadeer was argued to teach a method for determining a memory’s minimum operating voltage using a Built-In Self-Test (BIST) circuit and storing that value in non-volatile memory, such as fuses. Zhang was asserted to teach using integrated voltage regulators to provide adjustable, regulated voltages to different components of an IC to manage power consumption.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to create a more robust and efficient power management system. A POSITA would apply Abadeer’s technique for determining a minimum operating voltage to define the vague "set level or threshold" in Harris, thereby creating a predictable and reliable trigger for switching to the standby voltage. Furthermore, a POSITA would incorporate Zhang's well-known voltage regulators to supply the stable and controllable voltages required by the Harris system, which is a standard engineering choice for implementing dynamic voltage scaling and improving performance.
  • Expectation of Success: Combining these known elements—a voltage switching architecture (Harris), a method to determine the voltage threshold (Abadeer), and standard voltage regulators (Zhang)—would have yielded the predictable result of an improved power management system with no technical hurdles.

Ground 2: Obviousness over Harris, Abadeer, Zhang, and Cornwell - Claims 2, 11, and 12 are obvious over the combination of Harris, Abadeer, Zhang, and Cornwell.

• Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), Zhang (Application # 2003/0122429), and Cornwell (Patent 7,702,935).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the base combination of Ground 1 to address claims requiring testing for specific types of minimum voltages (minimum read, write, and standby). While Abadeer taught testing for a minimum standby voltage, Petitioner argued that Cornwell explicitly disclosed determining and storing minimum operating voltages for specific memory functions, including "minimum voltage for read operation" and "minimum voltage for write operation."
  • Motivation to Combine: A POSITA seeking to fully optimize power savings across all modes of memory operation, not just standby, would have been motivated to look beyond Abadeer. Cornwell provided the explicit teaching to test for and use minimum read and write voltages to further minimize power consumption during active memory use. This would have been a natural extension of the power-saving goals of the primary combination.
  • Expectation of Success: A POSITA would have had a high expectation of success in incorporating Cornwell's function-specific voltage testing into the base system, as it applied known testing principles to achieve more granular and predictable power savings.

Ground 3: Obviousness over Harris, Abadeer, Zhang, and Bilak - Claim 8 is obvious over the combination of Harris, Abadeer, Zhang, and Bilak.

• Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), Zhang (Application # 2003/0122429), and Bilak (Application # 2005/0188230).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground targeted claim 8, which specified that the minimum voltage determination is performed by a test "applied externally from the integrated circuit." Abadeer taught an internal BIST. Petitioner argued that Bilak explicitly taught determining the minimum operating voltage (Vmin) of an IC "during testing of the IC (typically by an external tester during manufacturing test)."
  • Motivation to Combine: Bilak presented external testing as a well-known and interchangeable alternative to internal BIST for determining minimum operating voltage. A POSITA would have understood that both internal and external testing were predictable, finite solutions for the same problem. Therefore, a POSITA would have been motivated to use the "well known" external testing method taught by Bilak as a design choice when implementing the system of Harris and Abadeer.
  • Expectation of Success: Since Bilak explicitly described external testing as a common and known technique, a POSITA would have reasonably expected to successfully apply this method to the base combination to determine the memory’s minimum operating voltage.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise discretionary denial under 35 U.S.C. §314(a) or §325(d). It contended that a previous IPR petition by Petitioner was denied solely under Fintiv factors and not on the merits of the invalidity arguments. Petitioner further argued that because the trial in the parallel district court litigation had already concluded, and the issue of the ’373 patent’s invalidity was not presented to the jury, there was no risk of inconsistent outcomes or concerns of judicial economy that would favor denial.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-13 and 15-16 of the ’373 patent as unpatentable.