BMW Of North America LLC v. Arigna Technology Ltd

1. Case Identification

• Case #: IPR2022-00481
• Patent #: 7,049,850
• Filed: January 25, 2022
• Petitioner(s): BMW of North America, LLC
• Patent Owner(s): Arigna Technology Ltd.
• Challenged Claims: 1, 7, 8, 10, 13, and 20

2. Patent Overview

• Title: Semiconductor Device with a Voltage Detecting Device to Prevent Shoot-Through Phenomenon in First and Second Complementary Switching Devices
• Brief Description: The ’850 patent discloses a semiconductor device for driving a half-bridge switching circuit. The device incorporates a voltage detecting mechanism to prevent a "shoot-through" phenomenon, where high-side and low-side switching devices are simultaneously turned on, causing a damaging short-circuit.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1, 13, and 20 by Wong

• Prior Art Relied Upon: Wong (Patent 6,037,720).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Wong, which was not considered during prosecution, discloses every element of independent claims 1, 13, and 20. Wong describes a semiconductor switched-bridge circuit with high-side (T1) and low-side (T2) switching devices. It includes a high potential part with control circuitry and a low potential part with a logic circuit (ANO circuit 114) that generates control signals based on an external input to prevent shoot-through. Petitioner asserted that Wong’s pulse generator (134), level shift parts (current sources Iia/Iib and switches T3a/T3b), and voltage detecting device (falling edge detector FED and rising edge detector RED) map directly onto the corresponding limitations of claim 1. The voltage detecting device in Wong monitors the level shift parts to control the low-side logic circuit, satisfying the final limitation of claim 1. Petitioner contended that Wong similarly discloses the specific combinations of elements recited in claims 13 and 20.

Ground 2: Anticipation of Claim 7 by Orita

• Prior Art Relied Upon: Orita (Application # 2003/0012040).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Orita, also not considered during prosecution, anticipates each limitation of independent claim 7. Orita discloses a power semiconductor device with a half-bridge configuration (switches SW1 and SW2). It explicitly teaches a high potential part containing a control part (output circuit OU and level shift circuit LS) to control the high-side switch (SW1). Orita’s reverse level shift circuit (IS) is configured to shift a signal from the high potential part to the low-side logic circuit. Crucially, Petitioner argued that Orita’s inverter (IV3) functions as the claimed "voltage detecting device" located in the high potential part. This inverter detects a potential from the output of the reverse level shift circuit (via inverter IV1) and supplies a logic value to a flip-flop (FF1) that ultimately controls the high-side switch, thereby satisfying all limitations of claim 7.

Ground 3: Obviousness of Claims 8 and 10 over Orita in view of Sedra & Smith

• Prior Art Relied Upon: Orita (Application # 2003/0012040) and Sedra & Smith (a 1998 microelectronics textbook).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Orita teaches all elements of parent claim 7. Dependent claim 8 adds structural limitations for the voltage detecting device, requiring at least one MOS transistor with a gate insulating film. Claim 10 further specifies that the MOS transistor is a complementary MOS (CMOS) transistor (NMOS and PMOS). Petitioner argued that while Orita discloses the function of the voltage detecting device (inverter IV3), it does not specify its implementation. Sedra & Smith, a standard textbook, extensively details the design and structure of CMOS inverters, including the use of MOS transistors, gate insulating films (SiO2), and the complementary pairing of NMOS and PMOS transistors.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would have been motivated to implement Orita's generic inverter (IV3) as a standard CMOS inverter as taught by Sedra & Smith. CMOS technology was the predominant, preferred implementation for digital logic circuits at the time due to its reliability, low power consumption, and low manufacturing cost, aligning with Orita’s stated goals.
  • Expectation of Success: A POSITA would have had a high expectation of success because implementing a logical inverter using a well-understood, textbook-standard CMOS structure was a routine and predictable design choice. This combination involved applying a known technique to a known device to yield predictable results.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv is unwarranted. It asserted that it acted diligently by filing its petition to seek joinder with a previously filed petition (IPR2022-00147) before its institution. Furthermore, the co-pending district court litigation was in its early stages, with minimal investment of resources, and the IPR addresses more claims than are at issue against Petitioner in the litigation.
• Petitioner also argued against denial under §325(d), emphasizing that none of the asserted prior art references (Wong, Orita, Sedra & Smith) were considered by the examiner during the original prosecution of the ’850 patent. Therefore, the petition raises new, non-cumulative arguments that were not previously before the USPTO.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 7, 8, 10, 13, and 20 of the ’850 patent as unpatentable.