Samsung Electronics Co Ltd v. Bishop Display Tech LLC

1. Case Identification

• Case #: IPR2022-00501
• Patent #: 7,995,047
• Filed: January 31, 2022
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Bishop Display Tech LLC
• Challenged Claims: 1-4, 9, 10

2. Patent Overview

• Title: Current Driving Device
• Brief Description: The ’047 patent discloses a current driving device for displays, such as organic light-emitting diode (OLED) panels, designed to address non-uniformity in display images caused by variations in transistor fabrication. The invention adds a voltage supply source to a prior art circuit to perform a high-speed "pre-charge" calibration, which improves the speed and uniformity of output currents.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Shimoda - Claims 1-4 and 9 are anticipated by, or are obvious over, Shimoda.

• Prior Art Relied Upon: Shimoda (a 2003 journal article from the Society for Information Display).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Shimoda discloses every limitation of claims 1-4 and 9. Shimoda addresses the same problem of non-uniformity in display driver circuits and teaches adding a "pre-charge circuit" to reduce current-programming times, which corresponds to the ’047 patent's claimed invention. Petitioner mapped Shimoda's pre-charge circuit to the claimed "first voltage supply source," its current source to the "first current supply source," and its pixel circuits to the "current output circuits." Furthermore, Petitioner asserted Shimoda teaches the required three modes of operation: a pre-charge period (voltage supply mode), a current-programming period (current supply mode), and an emission period (current output mode). Dependent claims 2-4 were also argued to be disclosed, covering the parallel connection of circuits and the actuation and stopping of the current-voltage conversion under different modes.
  • Motivation to Combine (for §103 grounds): As this ground was primarily based on anticipation under 35 U.S.C. §102, the motivation is inherent in the single reference. The alternative obviousness argument relied on the same teachings.
  • Expectation of Success (for §103 grounds): Since Shimoda allegedly discloses a complete, working circuit, a POSITA would have had a complete expectation of success.

Ground 2: Anticipation and Obviousness over Baek - Claims 1-4 and 9 are anticipated by, or are obvious over, Baek.

• Prior Art Relied Upon: Baek (Application # 2006/0170629).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Baek, which discloses a display driver circuit for OLED panels, anticipates or renders obvious claims 1-4 and 9. Similar to the ’047 patent, Baek adds a pre-charge circuit to a conventional driver to reduce charge time. Petitioner mapped Baek’s "pre-charge circuit 350" to the "first voltage supply source" and its "current digital-to-analog converter (DAC) 330" to the "first current supply source." The "current sample/hold output circuits" in Baek were identified as the claimed "current output circuits." Petitioner further argued Baek’s timing diagrams show the three required operation modes (voltage supply, current supply, and current output) corresponding to different control signals (C_PRE, CLK, and LE).
  • Motivation to Combine (for §103 grounds): The motivation is inherent in the single reference, as Baek was presented as a complete system that addresses the same technical problems as the challenged patent.
  • Expectation of Success (for §103 grounds): A POSITA would have expected success because Baek provides a detailed disclosure of an operational circuit.

Ground 3: Anticipation and Obviousness over Sasaki - Claim 10 is anticipated by, or is obvious over, Sasaki.

• Prior Art Relied Upon: Sasaki (Application # 2005/0017765).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Sasaki discloses all limitations of claim 10. Sasaki describes a current generation supply circuit that recognizes issues with current variations and lengthy charge times. Petitioner mapped Sasaki's "current supply source control transistor TP36" to the claimed "current input switch." The "charge storage circuit" including capacitor Ca was mapped to the "voltage holding circuit," and the "refresh control transistor Tr10" was identified as the "calibration switch." The "module current transistors" (TP12-TP15) were argued to be the claimed "plurality of voltage-current converting elements," and the switching transistors (TP16-TP19) were mapped to the "signal response switches."
  • Motivation to Combine (for §103 grounds): The argument was based on anticipation, making the motivation inherent to the single reference teaching all claimed elements.
  • Expectation of Success (for §103 grounds): Success was expected as Sasaki describes a functional circuit for driving display pixels.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §325(d) is unwarranted because none of the asserted prior art references (Shimoda, Baek, or Sasaki) were previously considered by the USPTO during prosecution.
• Petitioner also contended that discretionary denial under Fintiv is inappropriate. The key arguments were that the parallel district court litigation is at a very early stage with an uncertain trial date due to the large number of asserted patents (13), and the Petitioner offered a broad stipulation to prevent overlap of invalidity issues between the IPR and the district court case. Petitioner also argued the merits of the petition are strong, favoring institution.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 9, and 10 of the ’047 patent as unpatentable.