Microsoft Corp v. ThroughPuter Inc

1. Case Identification

• Case #: IPR2022-00528
• Patent #: 9,424,090
• Filed: February 4, 2022
• Petitioner(s): Microsoft Corp.
• Patent Owner(s): ThroughPuter, Inc.
• Challenged Claims: 1-7, 9-15

2. Patent Overview

• Title: Scheduling Tasks to Configurable Processing Cores Based on Task Requirements and Specification
• Brief Description: The ’090 patent discloses a "type adaptive manycore processor architecture" for managing processing tasks. The system dynamically assigns tasks from multiple applications to an array of processor cores that can be reconfigured (e.g., FPGAs) to match the specific requirements of each task, thereby improving processing efficiency.

3. Grounds for Unpatentability

Ground 1: Claims 1-5 and 7 are obvious over Chen in view of Agrawal.

• Prior Art Relied Upon: Chen (a 2004 conference paper on FPGA scheduling) and Agrawal (a 2007 symposium paper on adaptive scheduling).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chen taught a method for assigning tasks to regions of a reconfigurable FPGA array. Chen’s primary goal was to maximize "configuration reuse" by selecting tasks that fit into already-configured regions, thus minimizing the costly reconfiguration process. This maps to the core limitations of assigning tasks to an array of configurable cores and maximizing cores that do not need reconfiguration between tasks.
  • Motivation to Combine: Agrawal taught an adaptive scheduling system for parallel jobs that breaks time into a sequence of equal-sized "scheduling quanta." During these periods, processors are allocated to jobs. A person of ordinary skill in the art (POSITA) would combine Agrawal's use of scheduling quanta with Chen's system to create discrete periods for making scheduling decisions. This combination would allow for periodic optimization of task assignments to hardware resources, aligning with Chen's goal of minimizing reconfigurations between these consecutive quanta.
  • Expectation of Success: Success was expected because both references addressed space-sharing scheduling for parallel processing and used greedy heuristics. Applying a known time-slicing technique (quanta) from Agrawal to Chen's space-sharing system was a predictable way to improve scheduling performance.

Ground 2: Claims 3 and 4 are obvious over Chen, Agrawal, and Compton.

• Prior Art Relied Upon: Chen, Agrawal, and Compton (a 2002 survey article on reconfigurable computing).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Chen and Agrawal combination to address dependent claims 3 and 4, which required configuring a core to provide a "direct hardware logic implementation" of a task without "executable program instructions." Petitioner asserted that the Chen/Agrawal combination established the overall scheduling method. Compton was added because it explicitly described how reconfigurable hardware like FPGAs work at a fundamental level, explaining that custom digital circuits are mapped directly onto logic blocks, which constitutes a direct hardware implementation.
  • Motivation to Combine: A POSITA implementing the scheduling system of Chen and Agrawal on an FPGA would have been motivated to consult a reference like Compton for its foundational teachings on how such hardware is configured. Since Chen modeled its system as an array of configurable blocks, Compton provided the well-known explanation for how those blocks are programmed to perform specific tasks directly in hardware, which was necessary to render claims 3 and 4 obvious.
  • Expectation of Success: The combination was predictable because Compton merely provided explicit, well-understood details about the underlying hardware technology (FPGAs) that was the subject of the primary reference, Chen.

Ground 3: Claims 1, 2, 5-7, and 9-15 are obvious over Chen, Agrawal, and Brent.

• Prior Art Relied Upon: Chen, Agrawal, and Brent (Application # 2010/0131955).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Brent to the Chen/Agrawal combination to address limitations related to task selection based on specific demands and priorities. Petitioner argued Brent taught a multi-core system with an adaptive scheduler that used a "parallel task list." This list contained explicit details for each task, including its priority, its required data inputs, whether those inputs were currently available, and a "preferred core type for optimal execution." This provided a more detailed and explicit basis for the claim limitations requiring task selection based on core type demands and program-specific capacity indications.
  • Motivation to Combine: While Chen taught selecting a task that "fits well" in a region, it did not explicitly detail how to weigh various factors. A POSITA seeking to implement a robust version of the Chen/Agrawal scheduler would combine it with Brent's use of a detailed parallel task list. Brent's approach provided an explicit framework for considering factors like data dependency and preferred core types, making the scheduling decisions more effective and resolving ambiguities in Chen’s higher-level description.
  • Expectation of Success: The combination was predictable because implementing a scheduler with a priority list that considers data availability and hardware affinity, as taught by Brent, was a known and logical method for improving the performance of any task scheduling system, including the one derived from Chen and Agrawal.

4. Key Claim Construction Positions

• The petition proposed a construction for the term "an array of processor cores of configurable types" (claims 1 and 9).
• Petitioner argued a POSITA would understand this term to mean "an indexed set of discrete, reconfigurable hardware elements for processing." This construction was supported by the patent's own references to reconfiguring portions (slots) of programmable logic devices like FPGAs and dictionary definitions of "array" as an indexed set of elements.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under Fintiv would be inappropriate.
• The core reasons asserted were that the parallel district court litigation was in its infancy with no trial date set, petitioner had stipulated it would not pursue in district court the same invalidity grounds raised in the petition (eliminating concerns of duplicative efforts), and the petition presented strong merits for unpatentability.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-7 and 9-15 of the ’090 patent as unpatentable under 35 U.S.C. §103.