Microsoft Corp v. ThroughPuter Inc

1. Case Identification

• Case #: IPR2022-00574
• Patent #: 10,318,353
• Filed: February 11, 2022
• Petitioner(s): Microsoft Corporation
• Patent Owner(s): ThroughPuter, Inc.
• Challenged Claims: 1, 2, 8-14, and 21-24

2. Patent Overview

• Title: Concurrent Program Execution Optimization
• Brief Description: The ’353 patent describes a multi-stage, many-core processor system designed to dynamically share tasks from multiple application programs and their instances. The system uses logic to periodically assign sets of application task instances to processing cores and employs techniques for prioritizing program instances for execution.

3. Grounds for Unpatentability

Ground 1: Obviousness over Stevens, Smetana, and Daly - Claims 1 and 2 are obvious over Stevens in view of Smetana, with claim 2 further obvious in view of Daly.

• Prior Art Relied Upon: Stevens (Application # 2005/0044344), Smetana (Patent 6,211,721), and Daly (Application # 2008/0222640).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Stevens, which teaches an "adaptive computing engine" (ACE) with a plurality of configurable "matrices" or "nodes," discloses the core limitations of claim 1. Each Stevens matrix was asserted to be a "processing stage," and each contains multiple "computation units" that function as the claimed "multiple processing cores." Tasks are distributed across these matrices, satisfying the "local task" and "active task instance" limitations. However, Stevens does not explicitly state its multiplexers are hardware resources. Petitioner contended Smetana, which discloses a hardware multiplexer design for low power consumption and propagation delay, remedies this deficiency. For claim 2, Petitioner asserted that while Stevens's inpipes/outpipes suggest a buffer, Daly explicitly teaches source-specific input queues for task scheduling, directly mapping to the limitation of a buffer specific to another task.
  • Motivation to Combine: A POSITA would combine Stevens with Smetana to implement the conceptual multiplexing elements of Stevens's ACE using a well-known, efficient hardware multiplexer design to achieve the benefits of a true hardware platform, such as reduced delay. A POSITA would further incorporate Daly's teachings to improve task scheduling in the Stevens system by using known source-specific buffering, which allows for better differentiation and prioritization of inputs from various upstream tasks.
  • Expectation of Success: The combination involved applying conventional hardware components (Smetana's multiplexer) and standard task scheduling techniques (Daly's queues) to a known processor architecture (Stevens), which would have resulted in a predictable improvement in system performance.

Ground 2: Obviousness over Kupferschmidt, Du, and Anderson - Claims 8, 13, 21, and 24 are obvious over Kupferschmidt in view of Du and Anderson.

• Prior Art Relied Upon: Kupferschmidt (Application # 2010/0333099), Du (Application # 2008/0201716), and Anderson (Application # 2005/0021931).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kupferschmidt provides the foundational system: a network-on-chip (NOC) with an array of multi-threaded processor "IP blocks" (the "array of processor cores") that execute instances of a pipelined software application. However, Kupferschmidt provides little detail on its thread scheduling logic. Du was introduced for its teaching of a thread scheduler that classifies threads into "active" or "sleep" states based on the availability of necessary resources, such as input data or instructions. This maps directly to the claimed method of "classifying the plurality of instances." Anderson was added to address the "set of priority classes" limitation, as it teaches a thread ranking unit that ranks active hardware threads based on metrics like "thread priority" to control instruction issuance. The combination of these references was argued to teach a control system that classifies instances based on whether they are waiting for input data or memory transfers, and then selects a subset of active, prioritized instances for execution.
  • Motivation to Combine: A POSITA would have been motivated to improve the thread management of Kupferschmidt's system to enhance efficiency. Du provided a known solution for preventing idle threads from consuming execution resources by classifying them based on resource availability. Anderson offered a complementary, known technique for further optimizing the system by prioritizing among the "active" threads to ensure that higher-priority tasks are executed first.
  • Expectation of Success: Combining these known thread scheduling and prioritization techniques from Du and Anderson with Kupferschmidt's multi-threaded processor architecture would have predictably improved resource utilization and overall system performance.

Ground 3: Obviousness over Kupferschmidt, Du, Anderson, and Daly - Claims 9-12, 14, 22, and 23 are obvious over the combination of Kupferschmidt, Du, and Anderson, further in view of Daly.

• Prior Art Relied Upon: Kupferschmidt, Du, Anderson, and Daly (as cited above).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the combination of Kupferschmidt, Du, and Anderson. Petitioner asserted that the additional limitations in claims 9-12 and dependent claims—relating to ranking data sources into priority levels and classifying instances based on waiting for data from a "high priority data source level"—are taught by either Kupferschmidt's disclosure of high-priority and regular-priority inboxes or are made obvious by Daly. Daly explicitly teaches establishing separate, prioritized queues for different users (i.e., data sources), which directly corresponds to ranking data sources into different priority levels.
  • Motivation to Combine: A POSITA, having already combined Kupferschmidt, Du, and Anderson, would have been motivated to incorporate Daly's source-specific priority queuing to further enhance the system's scheduling capabilities. This would allow the scheduler to make more granular decisions based not just on thread priority (from Anderson) but also on the priority of the data's source (from Daly), a known method for improving scheduling in multi-source environments.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under Fintiv, asserting that multiple factors heavily favor institution. The related district court litigation was described as being in its infancy, with no trial date set, minimal investment by the court, and no claim construction yet performed. Most significantly, Petitioner stipulated that if the IPR is instituted, it will not pursue in the district court any invalidity ground that was raised or could have been reasonably raised in the petition. This stipulation was argued to eliminate any concerns of duplicative efforts or inconsistent rulings between the two forums.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 2, 8-14, and 21-24 of the ’353 patent as unpatentable.