PTAB

IPR2022-00633

Amazon.com Inc v. Swarm Technology LLC

Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System and Method for Swarm Collaborative Intelligence Using Dynamically Configurable Proactive Autonomous Agents
  • Brief Description: The ’275 patent describes a distributed processing system comprising a controller, a task pool, and multiple co-processors. The co-processors are configured to proactively retrieve and execute tasks from the task pool without direct communication with the controller, working together to achieve a common objective.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lurie and Ethernet Specification - Claims 1, 3, 6, 11-12, 14, 16-17 are obvious over Lurie in view of Ethernet Specification.

  • Prior Art Relied Upon: Lurie (Application # 2007/0124363) and Ethernet Specification (a 1980 technical publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lurie discloses the core architecture of the challenged claims, teaching a distributed computing system with a controller (Technical Computing Client or TCC), a task pool (Automatic Task Distribution or ATD Mechanism), and multiple co-processors (Technical Computing Workers or TCWs). In Lurie, the TCWs proactively retrieve tasks from the ATD Mechanism and process them without direct communication with the TCC, thereby achieving a common objective (a "job"). Ethernet Specification discloses a standard protocol for local area networks (LANs) using data frames that contain source/destination addresses and a data payload, which Petitioner contended are analogous to the "agents" recited in the ’275 patent.
    • Motivation to Combine: Lurie's system is implemented on a network and discloses the use of LANs. Petitioner asserted a person of ordinary skill in the art (POSITA) would have been motivated to implement Lurie's LAN functionality using the ubiquitous and well-known Ethernet protocol. Doing so would be a simple application of a standard networking technology to implement the high-level system described by Lurie.
    • Expectation of Success: A POSITA would have had a high expectation of success in combining these references because it amounted to implementing a known distributed computing architecture (Lurie) over a standard, compatible, and widely-adopted network protocol (Ethernet).

Ground 2: Obviousness over Lurie, Ethernet Specification, and Andrews/Chow - Claims 2, 4, 7, 9-10, 13, and 15 are obvious over Lurie in view of Ethernet Specification, Andrews, and/or Chow.

  • Prior Art Relied Upon: Lurie (Application # 2007/0124363), Ethernet Specification (1980 technical publication), Andrews (a 2000 textbook), and Chow (Application # 2005/0132380).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon Ground 1 to address dependent claims. For claims 2, 7, and 13 (depositing/adding new tasks), Petitioner asserted that Andrews teaches a "bag-of-tasks" architecture where executing one task often generates new, smaller tasks that a worker process deposits back into the "bag" (task pool). For claims 4, 9, and 15 (determining available processing capacity), Petitioner asserted that Chow teaches co-processors that check the number of tasks in their local buffer to determine if they have capacity before fetching a new task from the queue.
    • Motivation to Combine: A POSITA would combine Andrews with Lurie to provide specific implementation details for how tasks are managed in a bag-of-tasks system, thereby improving load balancing and system efficiency. Similarly, a POSITA would combine Chow with Lurie to prevent co-processors from becoming overloaded or idle, a known problem in distributed computing that Chow’s buffer-checking mechanism addresses.

Ground 3: Obviousness over Lurie, Ethernet Specification, and Sander - Claim 5 is obvious over Lurie in view of Ethernet Specification and Sander.

  • Prior Art Relied Upon: Lurie (Application # 2007/0124363), Ethernet Specification (1980 technical publication), and Sander (Application # 2012/0192201).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground targets claim 5, which recites that the controller and task pool reside on a single monolithic integrated circuit (IC) that is separate from the co-processors. Petitioner argued that Sander explicitly discloses this architecture, teaching a CPU (controller) and a work queue (task pool) residing on one monolithic IC, while the co-processors are formed on separate substrates.
    • Motivation to Combine: A POSITA would combine Sander's hardware architecture with Lurie's functionally analogous system to gain known benefits. Placing the controller and task pool on a single IC, as taught by Sander, would decrease latency and prevent data loss, while keeping the co-processors separate would preserve the scalability and flexibility central to Lurie's system.
    • Expectation of Success: The combination was argued to be predictable, as it involved applying a known hardware configuration from Sander to a system with analogous software components and roles described in Lurie.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 8 based on the combination of Lurie, Ethernet Specification, Andrews, and Marjovi (a 2012 journal article), arguing Marjovi teaches using unmanned autonomous ground vehicles as co-processors in a distributed computing cluster to perform tasks like map merging.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under §314(a) and the Fintiv factors. It was asserted that the parallel district court actions were in very early stages, with one action stayed and the other having no trial date set. Petitioner contended that the merits of the petition are particularly strong and that the prior art combinations were not substantively considered during prosecution, weighing in favor of institution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-17 of Patent 10,592,275 as unpatentable.